MTL Fabrication

Useful Charts and Information

The purpose of this section is to present useful information and comparative charts of our machine and fab capabilities.

In general, unless explicitly indicated otherwise, ICL machines will accept 6” wafers only while TRL machines will accept 6” and smaller wafers, including pieces.

Diffusion
Metrology
Packaging
Photolithography
Vacuum
Wafer Cleans
TRL-Specific Issues
EML-Specific Issues

DIFFUSION

Charts and Summaries

High Temperature PROCESSES and some applications:

Oxidation:: Diffusion mask, MOS gate insulator, stress relief layer, silicon thinning.
Diffusion:: Doping, drive-in of implanted species.
Annealing:: Ion implant activation, reflow, recrystallization, sintering, film densification.
Low Pressure Chemical Vapor Deposition (LPCVD):: Stoichiometric and low stress silicon nitride, polysilicon, low temperature oxide (LTO)
Rapid Thermal Annealing (RTA):: Annealing of shallow ion implanted layers, contact alloying, silicidation, nitridation

CAUTIONS:

QUARTZWARE may be very hot, so HANDLE it with extreme care.
Avoid PARTICLE INHALATION FROM LPCVD REACTORS.

NOTE: High Temperature PROCESSES and WET CLEANS are the MOST PROBABLE sources of process CONTAMINATION so strict adherence to cleanroom protocols and wafer CLEANING procedures is critical.

The MAIN CONTAMINANTS are:

ALKALI METALS: SODIUM AND POTASSIUM ARE VERY MOBILE SPECIES even relatively LOW temperatures; THEY ARE VERY ABUNDANT IN NATURE AND VERY SOLUBLE IN WATER; THEY ARE RESPONSIBLE FOR INSTABILITY in SEMICONDUCTOR DEVICES
ORGANICS: CARBON COMPOUNDS HAVE A NEGATIVE EFFECT ON SEMICONDUCTOR JUNCTION PARAMETERS
METALS: Au. Cu, Fe generate DEEP LEVEL traps which degrade FREE CARRIER LIFETIME and CAUSE SOFT JUNCTION BREAKDOWN AND HIGH LEAKAGE CURRENTS in MOS and bipolar devices.

ICL Diffusion Equipment

CORAL Name	Dedicated to Process	Temp Ranges	Gases	Comments


5A-GateOx	Gate Ox	400-1050C	N2, O2, H2, N2O, Trans-LC	Internal Torch
5B-Anneal	Anneal	400-1050C	N2, O2, H2, Trans-LC	Internal Torch
5C-FieldOx	Field Ox	400-1050C	N2, O2, H2, Trans-LC	External Torch
5D-ThickOx	Thick Ox	400-1050C	N2, O2, H2, Trans-LC	External Torch

6A-nPoly	Phos Doped Polysilicon	550-650C	N2, SiH4, PH3	Flat Profile
6B-Poly	Polysilicon	550-650C	N2, SiH4	Tilt Profile
6C-LTO	LTO	350-450C	N2, O2, SiH4	Flat Profile
6D-Nitride	Nitride	700-800C	N2, NH3, SiH2Cl2	Tilt Profile

VTR	Low-stress Si Nitride	300-775C	N2, NH3, SiH2Cl2	Vertical Reactor, operated by staff only

RTA2	Ion Implant Anneal	400-1100C, 200 C /min	N2	TC & Pyrometer control

RTP	Ion Implant Anneal	400-1100C, 200 C /min	N2,O2,N2O,NH3	Pyrometer control

rcaICL	Cleaning Station

TRL Diffusion Equipment

CORAL Name	Dedicated to Process	Temp Ranges	Gases	Comments


A1-GateOx	Gate Ox	400-1050C	N2, O2, H2, Trans-LC	Internal Torch
A2-WetOxBond	Wet Ox Bond	400-1050C	N2, O2, H2	Internal Torch
A3-Sinter	Sinter	300-600C	N2, Forming Gas	H2 Flow Interlock
A4-Polyiamide	Polyimide	150-800C	N2, Ar
B1-Au	Au	400-1050C	N2, O2, H2, Ar	Internal Torch
B2-Ox-Alloy	Ox-Alloy	400-1050C	N2, O2, H2	Internal Torch
B3-DryOx	Dry Ox	400-1050C	N2, O2

B4-Poly	Polysilicon	560-630C	N2, SiH4	Flat Profile



rta35	Compound Semiconductors	300-1100C, 200 C /min	N2	TC & Pyrometer control

rcaTRL	Cleaning Station

METROLOGY

The following is a list of MEASURING INSTRUMENTS and what they determine:

UV1280: FILM thickness
P10 PROFILOMETER: STEP height
C-V PLOTTER: Capacitance-vs-voltage (C-V); used for OXIDE QUALITY EVALUATION
SCA :SURFACE CHARGE ANALYZER); used for OXIDE QUALITY EVALUATION
NANOSPEC: FILM THICKNESS
4-POINT PROBE: RESISTIVITY
MERCURY PROBE: C-V AND SCHOTTKY DIODE characteristics
WYKO: Phase shift interferometer for surface mapping;Topo-3D Software
FLX (model-2320): Thin Film Stress Measurement

PACKAGING

Wire Bonding

The ball–wire bonder is used to attach gold wire interconnects from a die to a die package lead in a predetermined manner. Pads to be bonded should be a minimum of 100 microns in size. Gold or aluminum bonding pads are recommended for this bonding application.Threading the tip can be the most challenging part of Using the wire-bonder.

Die Saw

The die saw is capable of sectioning wafers from 0.500 inch to 6 inches in diameter; also from a single wafer to a bonded stack of up to 11 wafers. All parameters for sectioning a die must be determined and programmed into the touch-pad controller prior to cutting the wafer.

CMP

Chemical mechanical polishing is used to planarize interlevel dielectric materials, or planarize thin films such as oxides, nitrides, polysilicon. There is a separate machine for planarizing copper and tungsten thin films. The process uses a polishing pad combined with a chemically-active slurry compound. A polyvinyl alcohol (PVA) sponge is used to remove residual slurry and clean the wafers after the CMP process. These tools are set up to run 6" wafers.

PHOTOLITHOGRAPHY

Photo processes include contact and projection lithography, wafer bonding (thermocompression, anodic, fusion and Si-direct), SU8 and polyimide patterning. Scanning e-beam lithography for smaller features is available in the SEBL[link to SEBL section which shld be in”affiliated labs”] shared facility. PMMA spinning and developing capabilities can be found in TRL

Exposure Tools

In ICL: i-stepper: is a Nikon stepper, 5X, i-line (365 nm), 0.4 µm resolution, 22mm x 22mm field size, die by die alignment, 0.01 µm alignment accuracy
In TRL: EV1: is an EVG620 contact mask aligner, i-line (365 nm), backside alignment, sub-micron resolution

ksaligner2: is a Karl Suss MA4 contact mask aligner, g-line (320 nm), IR backside alignment; 4” exposure field, sub-micron resolution

Photoresists in use in all fabs:

Thin Resist:: OCG 825-20cs
SPR 700-1.0
Thick Resist:: AZ 9260
Image Reversal Resist:: AZ 5214-E
SU-8 2000 series and DuPont polyimide

VACUUM

High vacuum processes include:

Deposition:: Plasma-enhanced Chemical Vapor Deposition (PECVD): of dielectric films, poly & amorphous Si
Physical Vapor Deposition (PVD):: mostly metals, some nitrides
Electron Beam Evaporation:: mostly metals, some oxides
Sputtering:: mostly metals, some oxides

Etching:

Reactive Ion Etching (RIE):: of dielectrics, Si & metals, up to a few microns deep
Deep Reactive Ion Etching (DRIE):: of Si, tens to hundreds of microns, including fully through the wafer

ICL Vacuum Equipment:

AMAT AME5000 (RIE): 2 chambers
Chamber A: oxide, nitride, dielectric etch
Chamber B: polysilicon & shallow silicon etch
AMAT Centura 5300 (HDP etch): 1 chamber
Oxide, nitride, dielectric high density plasma etch
LAM490B (RIE): Poly/Nitride/Shallow Silicon Etch
(4” wafers allowed if mounted on 6” handle wafer)
LAM Rainbow 9600 (TCP etch): 1 chamber
CMOS compatible metal etcher with integrated plasma strip and DI rinse for corrosion protection.
AMAT Endura (PVD): 4 chambers
CMOS metal sputtering:
Al, Ti, W, TiN
Novellus Concept One(PECVD): 1 chamber
deps Oxide, Nitride, Oxynitride, PSG, TEOS (up to several microns thick)
e-beamCMOS: Temescal (Electron Beam Evaporator)
CMOS-compatible Metals (Al, Ti, AlSi)

TRL Vacuum Equipment:

STS-CVD (PECVD): Deposits: Nitride, Oxide and Amorphous-Silicon
4” Gold-contaminated tool
(Pieces Ok on handle wafer)
STS1 (ICP DRIE): Etches Silicon 100s um deep features
4” Gold-contaminated tool
(Pieces Ok on handle wafer)
STS2, STS3 (ICP DRIE): Etches Silicon 100s um deep features
(Pieces Ok on handle wafer)
PLASMAQUEST (ECR RIE): Etches: Nitride, Oxide, Aluminum, Silicon, III/Vs Deposits: Nitride, Oxide and Amorphous-Silicon
4” Gold-contaminated tool
(Pucks and pieces OK)

Note: PECVD mode is discouraged – use STS-CVD instead
Perkin-Elmer (sputter): Metal sputter deposition, currently available:
Target 1: Al
Target 2: Ti
Target 3: Au
4”, 6” gold contaminated tool
(Pieces OK)
e-beamAu: Temescal (Electron Beam Evaporator)
Metals (Au, Ni, W, Cr, Ti, etc) and Dielectrics (eg, SiO2, Al2O3)
XeF2: Isotropic Silicon etcher.
Highly selective to Oxide, Nitride, Aluminum or Photoresist.
Gold-contaminated tool
(Accepts any size or piece up to a 6” wafer)

WAFER CLEANS

At various stages of their processing, wafers require wet-cleaning. The primary wet-clean steps are carried out in the “premetal” sink in ICL and the “acid-hoods” in TRL Using color-coded beakers. The RCA clean is done in the “RCA” stations, or in beakers in the “acid-hoods” in TRL (see RCA below – link to the paragraph starting ” The procedure RCA…”).

Note: Fab wipes should not be used as liners on wet bench surfaces or allowed to be wetted by acids or solvents.

The machine “pre-metal” is a sink in ICL that contains two beakers for piranha clean: one blue, for gross strip of photoresist, and one green for wafers free of resist. It also has a filtered HF 50:1 bath.

The procedure piranha consists of a 10-minute etch in the blue beaker of “pre-metal”.

The procedure pre-metal clean consists of a 10-minute etch in the green beaker of “pre-metal” followed by a 15-second etch in the HF bath of “pre-metal”.

The procedure double-piranha consists of a blue piranha followed by a green piranha

These cleans can be carried out in TRL in “acid-hood” or “acid-hood2”, Using appropriately color-coded beakers.

The procedure RCA consists of an organic clean and an ionic clean, SC-1 and SC-2. It is the most rigorous pre-diffusion clean and is described in the Diffusion SOPs.

Several types of cleanings must be done before and/or after certain steps as follows:

To remove resist: do an ash step followed by piranha clean (in the blue tank in “premetal” if in ICL)
Wafers returning from ion implantation, must receive an ash+ double piranha if they have resist or a double piranha alone if they are resist-free.
Prior to a diffusion step, wafers must receive an RCA step, no more than 4 hours in advance (unless they are coming directly from a tube on the same day).
Prior to endura, concept1, ICL e-beam, DCVD, wafers must receive a pre-metal clean
After CMP, wafers must receive a double piranha+HF dip (skip HF if wafers cannot tolerate it).
After TMAH, wafers must receive a piranha+HF dip (skip HF if wafers cannot tolerate it).
After KOH etch, wafers can only go directly into TRL. They must receive a Piranha+rinse in yellow beakers followed by piranha+rinse in green beakers plus a 50:1 HF dip if the wafers can tolerate it.
To remove the polymer left in wafers etched in any STS, the Bosch process must end in the SF6 cycle, and wafers must be ashed.
Wafers with exposed Ge cannot tolerate RCA cleans. An acceptable substitute is the following PTC-approved clean:

Note that the 50:1 HF:H2O is dilute enough to etch SiO2 very slowly (~5nm/min).

All steps are done at room temperature.

NH4OH:H2O 1:4 (tank 1) for 5 min. to etch native oxide
rinse (rinser 1)
H2O2:H20 1:6 15sec to grow about 20A of GeO2 (tank 1)
rinse (rinser 1)
HF 30 sec
rinse (rinser 1)
HCl:H2O 1:4 30sec (tank 2)
rinse (rinser 2)
dry

Never wear the protective acid-gear away from the wet bench areas; never touch the interior of labware or process surfaces.

TRL-SPECIFIC ISSUES

TRL allows processing of CMOS-compatible (VLSI, MEMS) as well as III-V devices. Materials processed routinely include Silicon and III-V compounds, including Au-bearing wafers and wafer pieces.

Because of the more flexible process capabilities, there is less automation which can result in more processing-induced variation and contamination.

There is a color-coded scheme for distinguishing different levels of contamination [see trl_color_codes.html ]

Don't use equipment which is cleaner than your lot!

Always put all labware you use back on the shelf you took it from.

The following tools are for Gold-bearing use ONLY

diff tube B1
e-beam-Au
rta35
plasmaquest
perkin-elmer
STS-cvd
sts1
photo-wet-r
specific chucks of EV & KS aligners & coater
specific SRDs

The following tools in TRL are for CMOS-Compatible use ONLY

diff tubes A1 through A4
diff tubes B2 thru B4
photo-wet-l
rca

TRL COLOR CODE CHART

[ trl_color_codes.html ]

EML-specific issues

EML is meant to be a very flexible fab, for rapid prototyping and many materials, not necessarily compatible with Si or other semiconductor processes. Thus, no PTC approval is required for working in EML. Similarly, all wafers can go into all EML tools, regardless of the previous process steps they have undergone. However, because of this, EML wafers are barred from ICL and TRL.

For EML tools see “Machine Chart“

Microsystems Technology Laboratories

IMPORTANT NOTE: This content is no longer being actively updated and has been transitioned to the MIT.nano Facility Users site. Please go there for up to date and additional information.