All entries for tomas palacios

• Print This Page
• Download as PDF

MIT-MTL Center for Graphene Devices and Systems

• Leadership: Professor Tomas Palacios, Director

The MIT/MTL Center for Graphene Devices and Systems (MIT-CG) brings together, MIT researchers and industrial partners to advance the science and engineering of graphene-based technologies.

The center explores advanced technologies and strategies that enable graphene-based materials, devices and systems to provide discriminating or break-through capabilities for a variety of system applications ranging from energy generation and smart fabrics and materials, to RF communications and sensing. The MIT-CG supports the development of the science, technology, tools and analysis for the creation of a vision for the future of graphene-enabled systems.

Membership privileges for MIT-CG include:

Stay abreast of research developments in graphene
• Webcast of seminars
• Complimentary attendance to meetings
• Facilitated access to IP
Interact with students and faculty at MIT-GC events
• Industry Focus Day
• Resume book of graduating students
Participate in working groups of leading companies and researchers in defining the path forward for graphene
• Timely white papers on key issues
Collaborate with leading researchers on research that addresses today’s challenges
• Direct student projects on modeling in support of working group activities
• Pre-competitive teaming

Stress State Characterization of InAlN/GaN Nanoribbon HEMT Structures using Convergent Beam Electron Diffraction

GaN-based high electron mobility transistors (HEMTs) are an important platform for the realization of high-power, high-frequency devices.  Nanoribbon (NR) HEMT structures represent a novel route towards piezodoping by allowing external stresses to be applied in the plane of the active layer and have been shown to enhance carrier transport properties ^[1] .  This work uses transmission electron microscopy (TEM) and finite element analysis (FEA) to investigate the stress state of InAlN/GaN NR HEMT devices and explore the role of Al₂O₃ in stress generation.

NR structures were fabricated using top-down techniques and passivated with varying thicknesses of Al₂O₃.  TEM samples were obtained from the device structures by using focused ion beam techniques.  Using convergent beam electron diffraction, strain relaxation profiles were obtained by analyzing the splitting of higher order Laue zone lines contained in the [5 4 0] zone axis pattern.  Splitting profiles were also generated from FEA models of the HEMT structure for comparison.  Finally, device-sized structures were simulated to investigate the stress state of the active HEMT layers as a function of the oxide thickness.

Comparison of the experimental and simulated splitting profiles in Figure 1 shows not only that the FEA model correctly replicates overall splitting behavior and the dependence on sample thickness, but that it also consistently under-estimates the experimental results, suggesting an additional source of stress not present in the current model.  Models of device structures showed a compressive stress generated in the active HEMT layer upon the creation of a NR structure that becomes tensile when a layer of Al₂O₃ is applied, as shown in Figure 2.  The magnitude of the tensile stress approaches that of the planar structure as the thickness of the oxide increases.  This data correlates well with earlier published ^[1] electrical characterization of these structures considering the decrease in carrier concentration observed for a compressive strain ^[2] .



Figure 1: Comparison of experimental splitting profiles obtained using CBED and simulated profiles from FEA. Insets show dark-field scanning TEM image and schematic model of NR structure.



Figure 2: Stress in the active HEMT layer for both NR and planar structures as a function of oxide thickness calculated using FEA compared to sheet resistance data replotted from ^[1] .




1. M. Azize, A. L. Hsu, O. I. Saadat, M. Smith, X. Gao, S. P. Guo, S. Gradečak, and T. Palacios, “High-electron-mobility transistors based on InAlN/GaN nanoribbons,” IEEE Electron Device Letters, vol. 32, pp. 1680-1682, Dec 2011. [↩] [↩] [↩]
2. J. Kuzmik, “InAlN/(In)GaN high electron mobility transistors: Some aspects of the quantum well heterostructure proposal,” Semiconductor Science and Technology, vol. 17, pp. 540-544, June 2002. [↩]

Synthesis of Monolayer Hexagonal Boron Nitride on Cu Foil using Chemical Vapor Deposition

• Authors: K. K. Kim, A. Hsu, X. Jia, S. M. Kim, Y. Shi, M. Hofmann, D. Nezich, J. F. Rodriguez-Nieva, M. Dresselhaus, T. Palacios, J. Kong
• Sponsorship: NSF, ONR GATE-MURI

Hexagonal boron nitride (h-BN) is very attractive for many applications, particularly as a protective coating, dielectric layer/substrate, transparent membrane, or deep ultraviolet emitter. In this work, we carried out a detailed investigation of h-BN synthesis on Cu substrate using chemical vapor deposition (CVD) with two heating zones under low pressure (LP). Previous atmospheric pressure (AP) CVD syntheses were able to obtain only a few layers of h-BN without a good control on the number of layers ^{[1] [2]} .  In contrast, under LPCVD growth, monolayer h-BN was synthesized, and time-dependent growth was investigated (Figure 1).  It was also observed that the morphology of the Cu surface affects the location and density of the h-BN nucleation (Figure 2).  Ammonia borane, which is easily accessible and more stable under ambient conditions than borazine, is used as a BN precursor. The h-BN films are characterized by atomic force microscopy, transmission electron microscopy and electron energy loss spectroscopy analyses. Our results suggest that the growth here occurs via surface-mediated growth, which is similar to graphene growth on Cu under LP. These atomically thin layers are particularly attractive for use as atomic membranes or dielectric layers/substrates for graphene devices ^[3] .



Figure 1: Monolayer h-BN characterization. (a) Optical image of h-BN on 300 nm SiO₂/Si. White dotted line indicates the border between h-BN and SiO₂. The inset displays a photograph of h-BN film on a quartz substrate (red dotted area). (b) Optical absorption spectra of a monolayer h-BN, monolayer graphene and a quartz substrate (as a reference). (c) TEM image of the folded edge of a monolayer h-BN.



Figure 2: Effect of copper surface morphology on h-BN growth. SEM images of (a) an unpolished copper foil and (b) a polished copper foil after h-BN growth for 10 min with T₁=70 ^oC. (c)-(d) AFM images of the unpolished copper foil after growth: (c) height and (d) phase images. (e) Height profile along the red dotted in (c) and (d).




1. Y. Shi, C. Hamsen, X. Jia, K. K. Kim, A. Reina, M. Hofmann, A. L. Hsu, K. Zhang, H. Li, Z.-Y. Juang, M. S. Dresselhaus, L.-J. Li, and J. Kong, “Synthesis of few-layer hexagonal boron nitride thin film by chemical vapor deposition,” Nano Letters, vol. 10, pp. 4134-4139, Oct. 2010. [↩]
2. L. Song, L. Ci, H. Lu, P. B. Sorokin, C. Jin, J. Ni, A. G. Kvashnin, D. G. Kvashnin, J. Lou, B. I. Yakobson, and P. M. Ajayan, “Large scale growth and characterization of atomic hexagonal boron nitride layers,” Nano Letters, vol. 10, pp. 3209-15, Aug. 2010. [↩]
3. K. K. Kim, A. Hsu, X. Jia, S. M. Kim, Y. Shi, M. Hofmann, D. Nezich, J. F. Rodriguez-Nieva, M. Dresselhaus, T. Palacios, and J. Kong, “Synthesis of monolayer hexagonal boron nitride on Cu foil using chemical vapor deposition,” Nano Letters, vol. 12, pp. 161-166, Jan. 2012. [↩]

300-GHz GaN Transistors

• Authors: D. S. Lee, E. Matioli, T. Palacios
• Sponsorship: DARPA NEXT Program, NSF CAREER Award, ONR DURIP Program

The unique combination of high electron velocity and high breakdown voltage of GaN makes this material an ideal candidate for high power and high frequency applications. Among the different possible nitride structures, an InAlN/GaN heterostructure is one of the most promising candidates for high frequency applications because the large polarization discontinuity between InAlN and GaN induces an extremely large charge density with barriers thinner than 10 nm.

This work reports lattice-matched In_0.17Al_0.83N/GaN high electron mobility transistors (HEMTs) on a SiC substrate with a record current gain cutoff frequency (f_T) of 300 GHz [1-2]. To suppress short-channel effects (SCEs), an In_0.15Ga_0.85N back-barrier is applied in an InAlN/GaN heterostructure for the first time. The GaN channel thickness is also reduced to 26 nm, which allows a good immunity to SCEs for gate lengths down to 70 nm, even with a relatively thick top barrier (9.4-10.4 nm). In a device with a gate length (L_g) of 30 nm, an on-resistance (R_on) of 1.2 Ω•mm, and an extrinsic transconductance (g_m.ext) of 530 mS/mm, a peak f_T of 300 GHz is achieved. An electron velocity of 1.37-1.45×10⁷ cm/s is extracted by two different delay analysis methods.



Figure 1: (a) Cross-sectional schematic of an InAlN/GaN HEMT with an InGaN back-barrier. (b) I_ds-V_ds characteristics of the devices with L_g = 30 nm.






1. D. S. Lee, X. Gao, S. Guo, D. Kopp, P. Fay, and T. Palacios, “300-GHz InAlN/GaN HEMTs with InGaN back-barrier,” IEEE Electron Device Letters, vol. 32, no. 11, pp. 1525-1527, Nov. 2011.
2. D. S. Lee, B. Lu, M. Azize, X. Gao, S. Guo, D. Kopp, P. Fay, and T. Palacios, “Impact of GaN channel scaling in InAlN/GaN HEMTs,” IEDM Technical Digest 2011, pp. 457-460, Dec. 2011.

Technology Development for GaN and Si Integration

• Authors: Z. Liu, T. Palacios
• Sponsorship: Singapore-MIT Alliance for Research and Technology

GaN is an excellent material to be used in high-power, high-frequency and high-temperature applications due to its wide band gap, high saturation velocity, etc. The monolithic integration of GaN power and/or high frequency devices with Si CMOS digital ICs would enable a new level of circuit design flexibility ^[1] . However, typically the GaN device fabrication uses different process technologies from the standard CMOS technologies in Si foundries, such as the Au-contained ohmic process. To realize the target of GaN and Si CMOS integration, Si-CMOS compatible process technologies need to be developed. For the first step, we endeavor to find an Au-free ohmic contact recipe with low contact resistance and smooth metal surface.

The samples we used in this work have a 3-nm GaN cap, a 20-nm unintentionally doped AlGaN barrier layer, and a GaN buffer layer grown on a 6-inch Si wafer. Mesa isolation was realized using ICP systems with Cl₂/BCl₃ gases. For the ohmic contact, we tried different metal schemes including Ti/Al, Ti/Al/Ti, Ti/Al/Pt, Ti/Al/Ni/Pt, Ti/Ge/Ti/Al/Ni/Pt, Si/Ti/Al/Ti/Ta, Mo/Al/Mo/Ti, Ta/Al/Ta, Ta/Al/Ni/Ta, etc, with different annealing temperatures varying from 500°C to 975°C using rapid thermal annealing (RTA) in N₂ ambience. We also tried to include a shallow recess using low etch-rate SiCl₄ plasma etch in an ICP system to improve the ohmic contact. Among these recipes, the metal scheme of Ti/Al/Ni/Pt is found to give a relatively low contact resistance with very good metal surface. Lower ohmic contact resistance values together with a smooth metal surface can be obtained if a 20-30-nm recess is added.

Figure 1 shows the optical pictures of the ohmic metal surface after RTA for 30 s for metal schemes of Ti/Al/Ni/Au, Ti/Al/Ni/Pt, and Ti/Al/Ni/Pt with recess. The Au-contained recipe shows a very rough surface even it is annealed at a relatively low temperature of 800°C. The intermixing of Al and Au and the formation of viscous AlAu₄ phase are believed to result in the rough surface ^[2] . Without Au, the metal surface of Ti/Al/Ni/Pt is very smooth even it is annealed at a much high temperature up to 950°C. The recess of 20 nm (and 30 nm, not shown here) has no obvious effect on the metal surface after annealing. Figure 2 shows the typical contact resistance (R_C) values measured using the transition length method (TLM). A low R_C of around 0.45 Ω-mm can be obtained for the normal Ti/Al/Ni/Au recipe. The R_C value of Ti/Al/Ni/Pt metal is higher (~2.0 Ω-mm), and it can decrease to 1.6Ω-mm with the recess of 20 nm. In the future, more work needs to be carried out to further lower the R_C and optimize the Au-free ohmic contact recipes.



Figure 1: The optical pictures of ohmic metal surfaces for AlGaN/GaN HEMTs. (a) Ti/Al/Ni/Au with RTA at 800°C; (b) Ti/Al/Ni/Pt with RTA at 950°C; and (c) Ti/Al/Ni/Pt with 20-nm recess and RTA at 950°C.



Figure 2: TLM results of the ohmic contact for AlGaN/GaN HEMTs. (a) Ti/Al/Ni/Au with RTA at 800°C; (b) Ti/Al/Ni/Pt with RTA at 950°C; and (c) Ti/Al/Ni/Pt with 20-nm recess and RTA at 950°.




1. H. S. Lee, K. Ryu, M. Sun, and T. Palacios, “Wafer-level heterogeneous integration of GaN HEMTs on Si (100) MOSFETs,” IEEE Electron Device Letters, vol. 33, no. 2, pp. 200-202, Feb. 2012. [↩]
2. A. N. Bright, P. J. Thomas, M. Weyland, D. M. Tricker, C. J. Humphreys, and R. Davies, “Correlation of contact resistance with microstructure for Au/Ni/Al/Ti/AlGaN/GaN ohmic contacts using transmission electron microscopy,” Journal of Appl. Phys., vol. 89, no. 6, pp. 3143-3150, Mar. 2001. [↩]

GaN-Based Transistors for Power Electronic Applications

• Authors: D. Piedra, B. Lu, M. Sun, E. Matioli, H.-S. Lee, T. Palacios
• Sponsorship: MIT GaN Energy Center, ARPA-E ADEPT, DOE GIGA, SRC/FCRP MSD, SRC/FCRP IFC

Wide band-gap III-nitride semiconductors have great potential for the next generation of power electronics. GaN high-electron-mobility transistors (HEMTs) in particular have attracted great interest due to their high breakdown electric field and high electron mobility. With lower conduction loss and higher switching frequency, GaN-based transistors can improve the efficiency and reduce the size of many power electronics systems.

The standard AlGaN/GaN HEMTs are depletion-mode transistors. However, normally-off transistors are preferred in power electronics. Recently, our group has developed a new normally-off tri-gate GaN metal-insulator-semiconductor-field-effect-transistor (MISFET) ^[1] . By using a three-dimensional tri-gate structure and a sub-micron gate recess, we achieve high performance normally-off GaN transistors with a breakdown voltage as high as 565 V at a drain leakage current of 0.6 μA/mm. The new tri-gate normally-off GaN MISFET has a maximum current density of 530 mA/mm and an on/off current ratio of more than 8 orders of magnitude with a sub-threshold slope of 86±9 mV/decade, as Figure 1 shows. We have also demonstrated a new multi-finger technology with higher yield and lower device resistance for InAlN/GaN HEMTs. A multi-finger device with gate width of 39.6 mm has an on-resistance (R_on) of 0.244 Ω and a maximum current of 18.5 A, as in Figure 2(a).

Finally, ion-implantation isolation technology has also been developed. A state-of-the-art 1800 V breakdown voltage with 2.2 mΩcm² specific on-resistance has been achieved on AlGaN/GaN HEMTs on Si substrate (Figure 2(b)). Devices with ion-implantation isolation have higher breakdown voltage than devices using mesa-etching isolation, showing that ion-implantation isolation is a promising candidate for the next-generation high voltage GaN-based HEMT fabrication.



Figure 1: (a) Transfer characteristics of a tri-gate normally-off GaN MISFET and a standard planar-gate D-mode GaN MIS-HEMT. Both devices have L_gs = 1.5 μm, L_g = 2 μm, L_gd = 10 μm and W = 100 μm. (b) Three-terminal breakdown voltage (BV) measurement of the tri-gate normally-off GaN MISFET with L_gd = 10 μm at V_gs = 0 V.



Figure 2: (a) I_d-V_d characteristic of a multifinger device with W_g = 39.6 mm and R_on = 0.244 Ω. (b) Three-terminal breakdown voltage as a function of L_gd for implantation and mesa devices. The inset shows the breakdown voltage at leakage current of 10 μA/mm




1. B. Lu, E. Matioli and T. Palacios, “Tri-gate normally-off GaN power MISFET,” IEEE Electron Device Letters, vol. 33, no. 3, pp. 360-362, 2012. [↩]

2D Crystals for Ubiquitous Electronics

• Authors: H. Wang, A. Hsu, L. Yu, K. K. Kim, Y.-H. Lee, Y. Shi, J. Kong, T. Palacios
• Sponsorship: SRC/FCRP MSD, ONR GATE-MURI, Institute for Soldier Nanotechnologies, Army Resarch Laboratory

Two-dimensional crystals, including graphene, hexagonal boron nitride, and transition metal dichalcogenides (TMD) materials, have outstanding properties for developing the next generation of electronic devices ^{[1] [2]} . Graphene is the first 2D crystal to attract attention. The symmetry of its honeycomb lattice structure confers on it unique transport properties. The advantages of graphene for radio-frequency (RF) applications derive in part from its high electron and hole mobility, which can exceed 200,000 cm²/Vs at T=5 K and 100,000 cm²/Vs at T=240 K ^{[3] [4]} , the highest ever reported for any semiconductor. Moreover, graphene is a zero-bandgap material in which the conduction and valence bands touch at a point called the Dirac point. In addition to zero bandgap, the density of states in graphene is zero at the Dirac point and increases linearly for energies above and below it, which allows for carrier modulation. The carriers in graphene are confined to a one-atom-thick layer, allowing unprecedented electrostatic confinement and making graphene flexible and transparent. The lack of bandgap can be compensated for by integrating it with other 2D materials such as MoS₂from the TMD family ^{[5] [6]} . MoS₂ shares many of graphene’s advantages for electronic applications; its 1.8 eV bandgap makes it ideal for building logic circuits to complement graphene.

This project demonstrates important building blocks for future integrated circuits based on 2D-materials on flexible substrates such as plastics, paper and textiles. These basic analog building blocks include ambipolar frequency multipliers ^{[7] [8]} , graphene RF mixers ^[9] , graphene oscillators, and graphene phased shift keying devices, plus technology for fabricating flexible devices and circuits on plastic substrates. We construct integrated logic circuits based on few-layer MoS₂, including an inverter, a NAND gate, a memory device, and a ring oscillator. Prototypes of these building blocks move towards new technologies that seamlessly integrate electronics into objects of daily life, from plastic and paper cups with integrated temperature sensors and clothing with embedded RF antennas to smart contact lenses that communicate with cell phones to display relevant information to the wearer.



Figure 1: (a) Schematic of the graphene FET device structure. (b) ambipolar IDS-VGS characteristics of the fabricated GFET. (c) SEM image of the device. (d) SEM image of the T-shape gate of a self-aligned graphene transistor.



Figure 2: (a) Application circuit of graphene frequency multipliers. (b) input (red) and output (black) signals of 6-GHz graphene frequency multiplier. (c) output signal spectrum of graphene RF mixer. (d) output spectrum of a graphene electrical oscillator.




1. A. K. Geim, “Graphene: Status and prospects,” Science, vol. 324, no. 5934, pp. 1530-1534, June 2009. [↩]
2. A. H. C. Neto, et. al., “The electronic properties of graphene,” Rev. Mod. Phys., vol. 81, pp. 109–162, 2009. [↩]
3. K. I. Bolotin, et al., “Ultrahigh electron mobility in suspended graphene,” Solid State Communications, vol. 146, no. 9, June 2008. [↩]
4. K. I. Bolotin, et al., “Temperature-dependent transport in suspended graphene,” Phys. Rev. Lett., vol. 101, 096802, 2008. [↩]
5. P. Joensen, R. F. Frindt, and S. R. Morrison, “Single-layer MoS₂” Mat. Res. Bull., vol. 21, pp. 457-461, 1986. [↩]
6. B. Radisavljevic, et. al., “Single-layer MoS2 transistors,” Nature Nanotechnology, vol. 6, pp. 147–150, 2011. [↩]
7. H. Wang, D. Nezich, J. Kong, and T. Palacios, “Graphene frequency multipliers,” IEEE Electron Device Lett., vol. 30, no. 5, May 2009. [↩]
8. H. Wang, et. al., “Gigahertz ambipolar frequency multiplier based on CVD graphene,” IEDM Tech. Digest, vol. 23, no. 6, pp. 572-575, 2010. [↩]
9. H. Wang, et. al., “Graphene-based ambipolar RF mixers,” IEEE Electron Device Lett., vol. 31, no. 9, Sept. 2010. [↩]

Reliability Studies of AlGaN/GaN HEMTs

• Authors: S. C. Tan, F. Gao, J. Joh, L. Li, T. Palacios, J. A. del Alamo, C. V. Thompson, S. C. Tan, F. Gao, J. Joh, L. Li, T. Palacios, J. A. del Alamo, C. V. Thompson

There is an increasing interest in AlGaN/GaN high electron mobility transistors (HEMTs) due to their great potential for high performance at microwave frequencies. However, the performance of these devices is often limited by material reliability issues. Unfortunately, a detailed physical understanding of the degradation mechanisms is still lacking. The objective of this project is to develop that understanding through appropriate testing and failure analysis, so that test methods and models can be developed that will lead to further improvement in the reliability and electrical performance of these devices though optimization their design.



Figure 1: Pits and particles observed at the gate edges of a stressed AlGaN HEMT (top view) ^[1] .

Recent work has focused on the formation of pits at the edge of the gate contact during electrical stressing and performance degradation ^{[1] [2] [3]} . These pits have been observed to form under a variety of stressing conditions and in a range of temperatures.  We have found that in some cases the pits are associated with formation of particles that appear to be an oxide of Ga (Figure 1), and that pit and particle formation is suppressed when samples are properly passivated or when they are stressed in ultra-high vacuum conditions. Also, stressing in the presence of water vapor was found to enhance the rate of degradation ^[1] .  This suggests that this failure mechanism is associated with electrochemically-enhanced oxidation.  We have also observed that the rate of pit formation is affected by temperature, both in isothermal experiments and in experiments in which the temperature within an individual device varies significantly.  This finding indicates that this failure process is thermally activated. We estimate an activation energy of about 0.3eV ^[2] .

Analytical techniques such as scanning electron microscopy (SEM), transmission electron microscopy (TEM), atomic force microscopy (AFM), cathode luminescence (CL), and energy-dispersive X-ray spectroscopy (EDX) will be employed in future studies of this and other degradation processes, with the goal of developing predictive models for failure rates and reliability.

1. P. Makaram, J. Joh, J. A. del Alamo, T. Palacios, and C. V. Thompson, “Evolution of structural defects associated with electrical degradation in AlGaN/GaN high electron mobility transistors,” Appl. Phys. Lett,  Vol. 96, p. 233509, 2010. [↩] [↩] [↩]
2. F. Gao, B. Lu, L. Li, S. Kaun, J. S. Speck, C. V. Thompson, and T. Palacios, “Role of oxygen in the OFF-state degradation of AlGaN/GaN high electron mobility transistors,” Appl. Phys. Lett., vol. 99, p. 223506, 2011. [↩] [↩]
3. L. Li, J. Joh, J. A. del. Alamo, and C. V. Thompson,“Spatial distribution of structural degradation under high-power stress in AlGaN/GaN HEMTs,” Appl. Phys. Lett., to be published. [↩]

Tomás Palacios

• Title: Emmanuel E. Landsman CD Associate Professor
• Department: Department of Electrical Engineering and Computer Science

Collaborators

• D. Antoniadis, MIT
• J. del Alamo, MIT
• P. Jarillo-Herrero, MIT
• D. Jena, University of Notre Dame
• J. Kong, MIT
• U. K. Mishra, University of California – Santa Barbara
• E. Monroy, CEA-Grenoble, France
• E. Munoz, ETSIT-UPM, Spain
• D. Perreault, MIT
• C. Thompson, MIT
• H. Xing, University of Notre Dame

Postdoctoral Associates

• M. Azize, France
• T. Fujishima, Japan
• T. Imada, Japan
• H.-S. Lee, South Korea
• Z. Liu, Singapore
• E. Matioli, Brazil

Graduate Students

• F. Gao, Research Assistant
• S. Ha, Research Assistant
• A. Hsu, Research Assistant
• D. S. Lee, Research Assistant
• S. Joglekar, Research Assistant
• B. Lu, Research Assistant
• B. Mailly, Research Assistant
• M. Medlock, Research Assistant
• D. Piedra, Research Assistant
• O. I. Saadat, Research Assistant
• M. Sun, Research Assistant
• H. Wang, Research Assistant
• L. Yu, Research Assistant
• X. Zhang, Research Assistant
• Y. Zhang, Research Assistant

Undergraduate Students

• B. Jain
• R. Luo

Support Staff

• J. Baylon, Admin Assistant II

Publications

Wang, H., A. Hsu, J. Kong, D. Antoniadis, and T. Palacios, “A Compact Virtual Source Current-Voltage Model for Top and Back-Gated Graphene Field Effect Transistors,” IEEE Trans. Of Electron Dev., vol. 58 (5), pp. 1523-1533, 11 pages, May 2011.

Lee, H.-S., D. S. Lee, and T. Palacios, “AlGaN/GaN High Electron Mobility Transistors Fabricated Through a Au-free Technology,” Electron Dev. Letts., vol. 32 (5), pp. 623-625, May 2011.

Ryu, K. K., J. Roberts, E. Piner, and T. Palacios, “Thin-body N-face GaN Transistor Fabricated by Direct Wafer Bonding,” Electron Dev. Letts., vol. 32 (7), pp. 895-897, July 2011.

Hsu, A., H. Wang, K. K. Kim, J. Kong, and T. Palacios, “High Frequency Performance of Graphene Transistors Grown by Chemical Vapor Deposition for Mixed Signal Applications,” Jap. J. of Appl. Phys., vol. 50(7), pp. 070114, 4 pages, July 2011.

Hsu, A., H. Wang, K. K. Kim, J. Kong, and T. Palacios, “Impact of Graphene Interface Quality on Contact Resistances and RF Device Performance,” Electron Device Letters, vol. 32(8), pp. 1008-1010, 3 pages, Aug. 2011.

Xiong C., W. Pernice, K. K. Ryu, C. Schuck, K. Y. Fong, T. Palacios, and H. X. Tang, “Integrated GaN photonic circuits on silicon (100) for second harmonic generation,” Optics Express, vol. 19 (11), pp. 10462-10470, 9 pages, 2011

Wang, H., T. Taychatanapat, A. Hsu, P. Jarillo-Herrero, and T. Palacios, “BN/Graphene/BN Transistors for RF Applications,” Electron Device Letters, vol. 32(9), pp. 1209-1211, 3 pages, Sept. 2011.

Lee, D. S., and T. Palacios, “500 GHz transistors based on GaN… when and how?,” Compound Semiconductor Magazine,pp.33-35, August/September 2011. (Invited).

Palacios, T., “Graphene Electronics: Thinking Outside the Si Box,” Nature Nanotechnology, vol. 6, pp. 464-465, 2 pages, 2011. (Invited).

Lee, D. S., X. Gao, S. Gao, D. Kopp, P. Fay, and T. Palacios, “300-GHz InAlN/GaN HEMTs With InGaN Back-Barrier,” IEEE Electron Dev. Letts.,vol. 32(11), pp 1525-1527, Nov. 2011.

Lu, B., T. Palacios, D. Risbud, S. Bahl, and D. I. Anderson, “Extraction of Dynamic On-Resistance in GaN Transistors under Soft- and Hard-switching Conditions,” Compound Semiconductors IC Symposium, Hawaii’s Big Island, HW, 4 pages, October 16-19, 2011. (Oral Presentation).

Lee, D. S., B. Lu, M. Azize, X. Gao, S. Guo, D. Kopp, P. Fay, and T. Palacios, “Impact of GaN Channel Scaling in InAlN/GaN HEMTs,” International Electron Device Meeting, Washington DC, December 5-7, 2011. (Oral Presentation).

Azize, M., O. Saadat, A. Hsu, M. Smith, S. Guo, S. Gradecak, and T. Palacios, “High Electron Mobility Transistors Based on InAlN/GaN Nanoribbons,” Electron Device Letters, vol. 32(12) pp. 1680-1682, Dec. 2011

Hoke, W. E., R. V. Chelakara, J. P. Bettencourt, T. E. Kazior, J. R. LaRoche, T. D. Kennedy, J. J. Mosca, A. Torabi, A. J. Kerr, H.-S. Lee, and T. Palacios, “Monolithic Integration of Silicon CMOS and GaN Transistors in a Current Mirror Circuit,” submitted to J. of Vac. Science and Tech. B, vol. 30(2) pp. 1-6, December 2011.

Palacios, T., “The coming of age of nanowire electronics,” Nature, vol. 481, pp 152-153, Jan 2012 (Invited).

Lee, H. S., K. Ryu, M. Sun, and T. Palacios, “Wafer-level Heterogeneous Integration of GaN HEMTs and Si (100) MOSFETs,” IEEE Electron Dev. Letts.,vol. 33(2), pp 200-202, Feb. 2012.

Lu, B., E. Matioli, and T. Palacios, “Tri-Gate Normally-off GaN Power MISFET,IEEE Electron Dev. Letts.,vol. 33(3), pp 360-366, March 2012.

Doping of Graphene Devices through Chlorination

• Authors: X. Zhang, K. K. Kim, J. Kong, M. Dresselhaus, T. Palacios

Graphene, a two-dimensional honeycomb lattice of sp²-hybridized carbon atoms, has attracted tremendous interest in the scientific community. Surface functionalization is a technology to engineer its electronic properties and make it even more desirable and controllable for electronic device applications. For example, chemical functionalization of graphene, especially by hydrogen, fluorine, and chlorine is predicted to enable doping, edge passivation, and opening of its bandgap. Here, we demonstrate that exposure of graphene device to chlorine plasma in an electron cyclotron resonance (ECR) plasma etcher is an effective way to tune the Fermi level of graphene carriers towards p-type direction, without sacrificing its high conductivity.

Figure 1 compares the Raman spectroscopy of graphene before and after chlorine plasma treatment and also shows how it changes after annealing. After chlorine plasma treatment for 30 s, the D band increases substantially while the G band blue shift by about 5 cm^-1. More importantly, the D band decreases significantly after a 30-min annealing at 500 °C, which means little defect creation occurs during the plasma process.  Further transport measurement shows that the carrier concentration in graphene increases considerably. The plasma reaction process tunes the Fermi level of an intrinsic p-type CVD graphene (V_Dirac >0) towards p-type direction further. We notice that the carrier mobility reduces after plasma reaction. However, this reduction should be mainly due to the increase of hole concentration in graphene rather than defect creation, which is confirmed by the decrease of its sheet resistance and increase of conductivity (see Figure 2). In addition, XPS analysis shows that the percentage of chlorine on the surface of graphene is around 20%. This approach indicates an important way to engineer graphene properties for high-performance applications of graphene devices.



Figure 1: Raman spectroscopy of graphene before plasma treatment, after plasma treatment, and after annealing.



FIgure 2: Comparison: conductivity, carrier concentration, mobility and sheet resistance of graphene devices before and after chlorination.




Graphene Chemical Sensors on Flexible Substrates

• Authors: B. Mailly-Giacchetti, F. Pappalardo, J. Kong, T. Palacios
• Sponsorship: STMicroelectronics, Institute for Soldier Nanotechnologies, International Iberian Nanotechnology Laboratory

With its all-surface 2D structure combined with very high carrier mobility, graphene is an extremely promising candidate for high sensitivity and low noise chemical sensing ^{[1] [2]} . Graphene devices can perform electrical detection for chemical sensing in many applications, e.g.,pH monitoring in electrolytes ^{[3] [4]} , measuring blood glucose, and in-vitro recording of the electrical activity of living cells ^[5] . Integrating graphene on plastic substrates ^[6] enables fabrication of low-cost, flexible sensors.

Our group has developed the first solution-gated graphene field effect transistor (SGFET) on a polyethylene naphthalate (PEN) substrate. These devices have important advantages with respect to traditional sensors, e.g., intrinsic signal amplification, simple electronic read-out, and straightforward integration with microelectronics. Fabrication of the SGFET starts with the transferring of graphene grown by chemical vapor deposition on the PEN substrate. Metal contacts were previously evaporated on the PEN substrate. Silicone rubber-based insulation was used to protect the metal contacts and wires from any contact with the electrolyte.

As Figure 2.a) shows, the characterization of our devices in a phosphate buffer solution demonstrates good transconductance, around 1 mS.mm^-1, and carrier mobility of 300 cm².V^-1.s^-1. Transconductance is 5 times smaller than that obtained for graphene on SiO₂ which is due to the 10 times rougher surface of PEN compared to SiO₂ and also the larger amount of PMMA residues remaining on graphene when transferred onto PEN. The pH measurements have been performed using these devices by recording how the Dirac point shifts with changes in pH, as Figure 2.b) shows. Sensitivity  to 22 mV/pH has been demonstrated. In addition, long-term pH monitoring was shown for the first time in these graphene devices, as Figure 2.c) shows. Our on-going work focuses on functionalizing graphene to demonstrate new biosensors for glucose and E. coli detection on plastic substrate.



Figure 1: a) Optical image of graphene chemical sensor array on plastic substrate. Inset on bottom right corner shows detail . b) Schematic of a graphene-on-PEN solution-gated transistor.



Figure 2: Transfer characteristics of 50×1000-µm² graphene-on-PEN SGFET at constant drain-source voltage of V_ds=50 mV for different pHs. b) Dirac point shift with pH. c) Drain-source current vs. time data for pHs 9-4.




1. M. Dankerl, M. V. Hauf, A. Lippert, L. H. Hess, S. Birner, I. D. Sharp, A. Mahmood, P. Mallet, J. Veuillen, M. Stutzmann, and J. A. Garrido, “Graphene solution-gated field-effect transistor array for sensing applications,” Adv. Funct. Mater., vol. 20, pp. 3117-3124, 2010. [↩]
2. L. H. Hess, M. V. Hauf, M. Seifert, F. Speck, T. Seyller, M. Stutzmann, I. D. Sharp, and J. A. Garrido, “High-transconductance graphene solution-gated field effect transistors,” App. Phys. Letters, vol. 99, p. 033503, 2011. [↩]
3. Y. Ohno, K. Maehashi, Y. Yamashiro, and K. Matsumoto, “Electrolyte-gated graphene field-effect transistors for detecting pH and protein adsorption,” Nano Lett., vol. 9, pp. 3318-3322, 2009. [↩]
4. J. Ristein, W. Zhang, F. Speck, M. Ostler, L. Ley and T. Seyller, “Characteristics of solution gated field effect transistors on the basis of epitaxial graphene on silicon carbide,” J. Phys. D: Appl. Phys., vol. 43, no. 34, p. 345303, 2010. [↩]
5. T. Cohen-Karni, Q. Qing, Q. Li, Y. Fang, and C. M. Lieber, “Graphene and nanowire transistors for cellular interfaces and electrical recording,” Nano Lett,, vol. 10, pp. 1098-1102, 2010. [↩]
6. S. Bae, H. Kim, Y. Lee, X. Xu, J. S. Park, Y. Zheng, J. Balakrishnan, T. Lei, H. R. Kim, Y. I. Song, Y. J. Kim, K. S. Kim, B. Ozyilmaz, J. H. Ahn, B. H. Hong, and S. Iijima, “Roll-to-roll production of 30-inch graphene films for transparent electrodes,” Naure. Nanotechnology, vol. 5, pp. 574-578, 2010. [↩]

Wafer-level Heterogeneous Integration of GaN HEMTs and Si (100) MOSFETs

• Authors: H.-S. Lee, M. Sun, K. Ryu, T. Palacios
• Sponsorship: DARPA, SRC/FCRP MSD

Nitride-based semiconductors have received considerable attention during the last decade due to their outstanding properties for opto-electronic, high frequency, and high power applications ^[1] . In addition to this remarkable performance, the high two-dimensional electron gas (2DEG) density and critical electric field of AlGaN/GaN allow a 10-fold increase in the output power density of GaN RF power amplifiers and high voltage electronics, when compared to state-of-the-art GaAs and Si circuits.

Our group has demonstrated a new technology for the heterogeneous integration of GaN and Si devices, which is scalable at least up to 4” wafers and compatible with conventional Si fabrication. The key step in the proposed technology is the fabrication of a Si (100)-GaN-Si hybrid wafer by bonding a silicon (100) on insulator (SOI) wafer to the nitride surface of an AlGaN/GaN on Si (111) wafer, as shown in Figure 1 (a). A thin layer of silicon oxide is used to enhance bonding between the SOI and AlGaN/GaN wafers. Using this technology, we have fabricated Si pMOSFETs and GaN HEMTs on a 4-inch hybrid wafer (see Figure 1 (b)). Due to the high thermal stability of GaN and the high quality semiconductor material resulting from the transfer method, the devices exhibit excellent performance. A hybrid power amplifier has been fabricated as a circuit demonstrator, which shows the potential to integrate GaN and Si devices on the same chip to enable new performance in high efficiency power amplifiers, mixed signal circuits, and digital electronics. Figure 2 shows a successfully fabricated AlGaN/GaN HEMT voltage amplifier circuit using a Si pMOSFET as a current source. The amplifier has a gain of 17 with 3 V supply voltage, as shown in Figure 2 (right).



Figure 1: (a) (left) Simplified schematic cross-sectional view and (right) SEM cross-sectional view of fabricated hybrid wafer. (b) (left) Photograph of a 4-inch hybrid wafer with fabricated GaN-Si devices. (right) Optical micrograph of a Si PMOSFET (L_g=2 μm, W=4 μm) and an AlGaN/GaN HEMT (L_g=2 μm, W=20 μm) fabricated in close proximity.



Figure 2: (left) Schematic of a GaN HEMT voltage amplifier that uses a Si pMOSFET as a current source. (center) An optical micrograph of the hybrid amplifier circuit. (right) Input and output waveforms of the GaN-Si hybrid amplifier.




1. D. S. Kuo, C. Shoou-Jinn, T. K. Ko, C. F. Shen, S. J. Hon, and S. C. Hung, “Nitride-based LEDs with phosphoric acid etched undercut sidewalls,” IEEE Photonics Tech. Letters, vol. 21, pp. 510-512, 2009. [↩]

Graphene Infrared Photodetectors

• Authors: L. Hsu, S. J. Ha, K. K. Kim, J. Kong, T. Palacios
• Sponsorship: ONR GATE-MURI, SRC/FCRP MSD, Institute of Soldier Nanotechnology



Figure 1: (a) Scanning electron microscopy (SEM) of bowtie array; (b) SEM of single element bowtie; (c) Fourier Transform infrared spectroscopy setup for characterization of graphene infrared photodetectors.

Graphene is a two-dimensional (2D) material that has attracted great interest for electronic devices since its discovery in 2004 ^[1] . With essentially the same lattice structure as an unwrapped carbon nanotube, graphene shares many of its advantages, such as having the highest intrinsic carrier mobility at room temperature of any known material ^[2] . This trait, combined with its high electron velocity and thermal conductivity, makes this carbon-based material an excellent candidate for high frequency electronic applications. Furthermore, graphene, due to its zero band gap band structure, also has a broadband optical absorption ranging from the far-infrared (λ>10 µm) all the way to the visible (λ< 532 nm) ^[3] . Standard state-of-the-art infrared focal plane arrays rely on very exotic materials systems such as InSb and HgCdTe, both of which are difficult to grow as well as difficult to integrate cheaply with silicon read out electronics ^[4] . Graphene, on the other hand, could enable a new generation of carbon-based infrared photodetectors.

Metal-graphene-metal photodetectors have been demonstrated in the visible range (532 nm) using exfoliated highly oriented pyrolytic graphite (HOPG); however, the external efficiencies of these devices are generally low (<1%) ^[5] . Graphene photodetectors may intrinsically have efficiencies ranging from 10-15%; however, poor optical coupling with the incident light reduces the overall efficiencies of these devices. Therefore, to better address these issues, we have begun fabrication of large area photodetector arrays utilizing plasmonic antenna elements to better match the incoming light to the spatial response of the graphene photodetectors designed in the infrared (Figure 1 (a) and (b)). Furthermore, using chemically vapor grown graphene, we have been fabricating large array photodetector arrays (1 cm x 1 cm) to better extract power from the incident electromagnetic radiation.  The setup for characterizing the optical properties of these photodetectors is shown in Figure 1(c).

1. K. S. Novoselov, et al., “Electric field effect in atomically thin carbon films,” Science, vol. 306, pp. 666-669, 2004. [↩]
2. Bolotin, et. al., “Ultrahigh electron mobility in suspended graphene,” Solid State Communications, vol. 146, pp. 351-355, 2008. [↩]
3. Z. Q. Li, et al., “Dirac charge dynamics in graphene by infrared spectroscopy,” Nature Physics, vol. 4, pp. 532-535, 2008. [↩]
4. A. Rogalski, “HgCdTe infrared detector material: History, status, and outlook,” Rep. Prog. Phys, vol. 68, p. 2267, 2005. [↩]
5. F. Xia, et al., “Ultrafast graphene photodetector,” Nature Nanotechnology, vol. 4, pp. 839-843, 2009. [↩]

Impact of Metal-induced Strain in InAlN/GaN Nanoribbons

• Authors: M. Azize, O. I. Saadat, T. Palacios
• Sponsorship: ONR, NSF

Nitride transistors with current gain cut-off frequencies (f_T) of 300 GHz and power gain cut-off frequencies (f_max) of 394 GHz have been reported ^{[1] [2]} . However, the frequency performance of these devices is still far from the theoretical limit due to poor gate modulation efficiency, short channel effects, high access resistances (R_a), and specific contact resistance (r_c). Nanoribbon (NR)-based nitride HEMTs could overcome many of these limitations by improving the electron confinement thanks to the excellent electrostatics of wrap-around gates ^[3] . Moreover, strong piezoelectric-induced doping can be generated in NR nitride-based semiconductors and increase the maximum operating frequency of nitride devices by reducing the parasitic resistances (Ra and r_c). In this project, we study the use of Ti-induced strain in InAlN/GaN NR HEMTs.

 NR and planar devices are fabricated on the same chip. A Ti/Al/Ni/Au metal stack is then deposited for ohmic contact formation. Electron beam lithography and dry etching are performed in some devices to define NR structures between the ohmic contacts with widths (w) in the w~20-90 ± 10 nm range and a period (p) of p~135 ± 10 nm. An additional Ti strip was deposited between the ohmic contacts (cf. inset of Figure 2) with a width of ~100 mm and a length varying from ~2 to 16 mm and annealed at 870 ^◦C for 30 s in N₂ environment. Figure 1 shows the total resistance R_T in NR and planar devicesas a function of the area coverage of the Ti stripes. A quasi-linear R_T decrease is observed when the Ti surface area increases in the InAlN/GaN NRs samples, unlike in the planar device. The mechanical stress introduced by Ti stripes has a strong effect on the transport properties of InAlN/GaN NRs. Figure 2 shows the decrease of the sheet resistance (R_shTi) underneath the Ti stripe in InAlN/GaN NRs as a function of NR widths. The R_shTi in the NR and planar devices is decreased by ~50-75 % and ~10%, respectively.



Figure 1: Total resistance in InAlN/GaN channel as a function of the area coverage of the Ti stripes. The inset shows a cartoon of NR and planar devices with different area coverage of the Ti stripes.



Figure 2: Sheet resistance underneath of the Ti metal stripes in InAlN/GaN devices as a function of the NR width. The inset shows a cartoon of NR and planar devices with identical area coverage of the Ti stripes.




1. D. S. Lee, X. Gao, S. Guo, D. Kopp, P. Fay, and T. Palacios, “300-GHz InAlN/GaN HEMTs with InGaN back barrier, IEEE Electron Device Lett., to be published. [↩]
2. K. Shinohara, D. Regan, I. Milosavljevic, A. L. Corrion, D. F. Brown, P. J. Willadsen, C. Butler, A. Schmitz, S. Kim, V. Lee, A. Ohoka, P. M. Asbeck, and M. Micovic, “Electron velocity enhancement in laterally scaled GaN DH-HEMTs with f_T of 260 GHz,” IEEE Electron Device Lett., vol. 32, no. 8, pp. 1074-10176, Aug. 2011. [↩]
3. W. Lu, P. Xie, and C. M. Lieber, “Nanowire transistor performance,” IEEE Trans. Electron Dev., vol. 55, no 11, pp 2859-2876, Nov. 2008. [↩]

Use of in-situ SiN_x to Reduce the OFF-state Degradation of AlGaN/GaN HEMTs

• Authors: F. Gao, S. Keller, U. K. Mishra, C. V. Thompson, T. Palacios
• Sponsorship: ONR DRIFT-MURI

Thanks to their excellent electrical performance, AlGaN/GaN high electron mobility transistors (HEMTs) are considered ideal devices for the next generation of high-power and high-frequency electronics ^[1] . However, the limited understanding of their long-term reliability and degradation mechanisms is slowing down the insertion of these devices in actual systems ^[2] .

Recently, we have reported the formation of oxide particles next to the gate edge of GaN HEMTs after OFF-state step-stress degradation experiments ^[3] . Underneath these particles, pits similar to the ones reported in previous papers ^[4] are observed. In this work, we investigate the role of oxygen in the formation of these particles/pits during OFF-state stress and use oxygen diffusion barriers to improve the reliability of AlGaN/GaN HEMTs.

Two different dielectrics have been used: Al₂O₃ deposited by atomic layer deposition and in-situ SiN_x deposited immediately after the growth of the AlGaN/GaN epitaxial layer by metal organic chemical vapor deposition (MOCVD). Step-stress degradation experiments were performed in both samples in air and vacuum. No degradation was found in either sample during the experiments in vacuum, which shows that the oxygen necessary for the particle formation probably comes from air. In contrast, when the samples were stressed in air, a large degradation and particle/pit formation were found in the Al₂O₃-passivated sample, while no structural or electrical degradation was found in the sample with in-situ SiN_x (see Figures 1 and 2). The in-situ SiN_x dielectric is believed to be a much better diffusion barrier for oxygen gas and water vapor than Al₂O₃, which significantly reduces device degradation.

In summary, the in-situ deposition of a SiN_x gate dielectric and passivation layer successfully eliminated the diffusion of oxygen from air and water vapor to the AlGaN surface, which improved the OFF-state reliability of AlGaN/GaN HEMTs.



Figure 1: Transfer characteristics of the device with ALD Al₂O₃ gate dielectric stressed at V_gs = -100 V and V_ds = 0 V for 6000 s in air and in vacuum. Permanent degradation of the drain current is observed in air.



Figure 2: Transfer characteristics of the device with in-situ SiN_x gate dielectric stressed at V_gs = -100 V and V_ds = 0 V for 6000 s in air. No current degradation is observed.




1. U. K. Mishra, L. Shen, T. E. Kazior, and Y-F Wu, Proceedings of the IEEE, 2008, vol. 96, p. 287. [↩]
2. G. Meneghesso, G. Verzellesi, F. Danesin, F. Rampazzo, F. Zanon, A. Tazzoli, M. Meneghini, and E. Zanoni, IEEE Trans. Device Mater. Reliab. vol. 8, p. 332, 2008. [↩]
3. F. Gao, B. Lu, L. Li, S. Kaun, J. S. Speck, C. V. Thompson, and T. Palacios, Appl. Phys. Lett. vol. 99, p. 223506, 2011. [↩]
4. J. Joh and J. A. del Alamo, IEEE Electron Device Lett. vol. 29, p. 287, 2008. [↩]

Graphene-based CMOS Infrared Imaging System

• Authors: S. Ha, A. Hsu, T. Palacios, A. P. Chandrakasan
• Sponsorship: International Iberian Nanotechnology Laboratory, MIT/Army Institute for Soldier Nanotechnologies, Fulbright Science and Technology Award

The CMOS image sensor is widely used in digital multimedia applications. Its performance ramps up every year with denser integration, better noise suppression, adjustable dynamic range, and lower power ^[1] . However, the band gap of silicon fundamentally limits the absorption spectrum to be in the visible and near-infrared light (λ < 1100nm) ^[2] . In our research, we propose an integrated CMOS imager with a graphene photodetector. With the zero band gap, the graphene photodetector absorbs long-wavelengths (λ > 1μm) and enables integrated circuits for a wide spectrum of imaging applications such as thermal and terahertz imaging.

In the design of the graphene photodetector, graphene’s high conductivity is a key problem. When a bias voltage is applied to a graphene photodetector, the resulting leakage current easily dominates the photocurrent. Also, the low output impedance severely limits the output voltage of the graphene photodetector up to only a few microvolts, which degrades the signal-to-noise ratio (SNR). To resolve the leakage issue and improve SNR, we propose to use a modulated input source. The mechanical shutter working at around 1 kHz shifts the input signal out from the DC region where the leakage component dominates. The modulation also suppresses flicker noise in the photodetector and the readout circuits, by a band-pass filter followed by a multi-stage low-noise amplifier.

Figure 1 shows the pixel design of the photodetector. Unlike p-n junction photodiodes ^[3] , the graphene photodetector is placed on top of the silicon substrate, requiring no extra area; as a result, higher integration can be achieved in each pixel. The amplitude of the photocurrent is measured by an 8b-resolution ADC in a column-parallel architecture as shown in Figure 2.  By multiplexing each pixel, this architecture gives a good trade-off between frame rate and power consumption.



Figure 1: Image sensor pixel design with graphene photodetector and low-noise amplifiers.



Figure 2: Top view of the floor plan of wide spectrum image sensor IC.




1. A. Fish and O. Yadid-Pecht, “Low power CMOS imager circuits,” in Circuits at the Nanoscale: Communications, Imaging, and Sensing, K. Iniewski, Ed. Boca Raton: CRC Press/Taylor & Francis, 2009. [↩]
2. R. Kaufmann, “Near infrared image sensor with integrated germanium photodiodes,” Journal of Applied Physics, vol. 110, pp. 023107-6, July 2011. [↩]
3. M. Perenzoni, N. Massari, D. Stoppa, L. Pancheri, M. Malfatti and L. Gonzo, “A 160×120-pixels range camera with in-pixel correlated double sampling and fixed-pattern noise correction,” IEEE Journal of Solid-State Circuits, vol. 46, pp. 1672-1681, July, 2011. [↩]