All entries for jesus del alamo

Jesús A. del Alamo

Title: Donner Professor, MacVicar Faculty Fellow
Department: Department of Electrical Engineering and Computer Science (EECS)

Collaborators

L.J. Brillson, Ohio State University
J. Jimenez, Triquint Semiconductor
D.H. Kim, Teledyne
T.-W. Kim, Global Foundries
B. R. Bennett, NRL

Postdoctoral Associates

A. Vardy, MIT-Technion Fellow

Graduate Students

A. Guo, NDSEG Fellowship
L. Guo, NSF Fellow
D.H. Jin, Samsung Fellow
J. Lin, RA EECS
W. Lu, RA EECS
S. Warnock, RA EECS
Y. Wu, RA EECS
X. Zhao, RA, DMSE

Support Staff

E. Kubicki, Administrative Assistant II

Publications

del Alamo, J. A., “Recent progress in understanding the DC and RF reliability of GaN high-electron mobility transistors.” Invited talk at Materials Research Society Spring Meeting, April 9-13, 2012.

Lin, J., T.-W. Kim, D. A. Antoniadis and J. A. del Alamo, “A Self-Aligned InGaAs Quantum-Well MOSFET Fabricated through a Lift-off Free Front-end Process.” Applied Physics Express, Vol. 5, p. 064002, May 16, 2012.

Jin, D. and J. A. del Alamo, “Mechanisms responsible for dynamic ON-resistance in GaN high-voltage HEMTs.” 24th IEEE International Symposium on Power Semiconductor Devices and ICs (ISPSD), June 3-7, 2012, pp. 333-346.

Kim, T.-W., R. J. W. Hill, C. D. Young, D. Veksler, J. Oh, C. Y. Kang, D.-H. Kim, J. A. del Alamo, C. Hobbs, P. Kirsch and R. Jammy, “InAs Quantum-Well MOSFET (Lg=100 nm) with Record High gm, fT and fmax.” 2012 Symposium on VLSI Technology, June 12-15, 2012, pp. 179-180.

del Alamo, J. A. and D.-H. Kim, “InAs High-Electron Mobility Transistors on the Path to THz Operation.” Invited paper at International Conference on Solid State Devices and Materials (SSDM), September 25-27, 2012.

del Alamo, J. A., “Nanometer-Scale III-V CMOS.” Short Course on the Future of Semiconductor Devices and Integrated Circuits at 34th IEEE Compound Semiconductor IC Symposium (CSICS), October 14, 2012.

Lin, C.-H., T. A. Merz, D. R. Doutt, J. Joh, J. A. del Alamo, U. K. Mishra, and L. J. Brillson, ”Strain and temperature dependence of defect formation at AlGaN/GaN high electron mobility transistors on a nanometer scale.” IEEE Transactions on Electron Devices, Vol. 59, No. 10, pp. 2667-2674, October 2012.

Lin, J., D. A. Antoniadis, and J. A. del Alamo, “Sub-30 nm In As Quantum-Well MOSFETs with Self-Aligned Metal Contacts and Sub-1 nm EOT HfO2 Insulator.” IEEE International Electron Devices Meeting, December 10-12, 2012, pp. 757-760.

Kim, T.-W. , R. J. W. Hill, D. Kim, D.-H. Koh, R. Lee, M. H Wong, T. Cunningham, J. A. del Alamo, S. K. Banerjee, S. Oktyabrsky, A. Greene, Y. Ohsawa, Y. Trickett, G. Nakamura, Q. Li, K. M. Lau, C. Hobbs, P. D. Kirsch and R. Jammy, “ETW-QW InAs MOSFETs with Scaled Body for Improved Electrostatics.” IEEE International Electron Devices Meeting, CA, December 10-12, 2012, pp. 765-768.

Jin, D. and J. A. del Alamo, ”Impact of high-power stress on dynamic ON resistance of high-voltage GaN HEMTs.” Microelectronics Reliability, Vol. 52, pp. 2875-2879 (2012).

Kim, D.-H., J. A. del Alamo, D. A. Antoniadis, J. Li, J.-M. Kuo, P. Pinsukanjana, Y.-C. Kao, P. Chen, A. Papavasiliou, C. King, E. Regan, M. Urteaga, B. Brar, and T.-W. Kim, ”Lg=60 nm recessed In0.7Ga0.3As metal-oxide-semiconductor field-effect transistors with Al2O3 insulator.” Applied Physics Letters, Vol. 101, p. 223507, 2012.

Kim, D.-H., T.-W. Kim, R. J. W. Hill, C. D. Young, C. Y. Kang, C. Hobbs, P. Kirsch, J. A. del Alamo, and R. Jammy, ”High-Speed E-Mode InAs QW MOSFET with Al2O3 Insulator for Future RF Applications.” IEEE Electron Device Letters, Vol. 34, No. 2, pp. 196-198, February 2013.

del Alamo, J. A. , “THz III-V HEMT Technology.” Short Course on THz Transistors and Packaging Integration Technologies, International Wireless Symposium, April 14-18, 2013.

Guo, A. and J. A. del Alamo, “Mo/n+-InGaAs Nanocontacts for Future III-V MOSFETs.” To be presented at 25th International Conference on Indium Phosphide and Related Materials, May 19-23, 2013.

Degradation of GaN HEMTs under High-power and High-temperature Conditions

Authors: Y. Wu, J. A. del Alamo
Sponsorship: Office of Naval Research MURI

Due to the wide band gap energy and high breakdown electric field of GaN, heterostructure transistors made from it are promising candidates for high power and high frequency applications. However, one issue that prevents the wide deployment of GaN HEMTs is their reliability. Research has been actively trying to improve the reliability of these devices. In spite of this, detailed understanding of the physics of device degradation mechanisms is still lacking^[1]. Our research aims to fill this gap.

Previous studies have shown that under OFF-state stress, GaN HEMT degradation is dominated by a defect formation mechanism through the inverse piezoelectric effect [1]. This research studies GaN HEMT degradation under a more practical stress condition, i.e., the high power state. Devices were biased at V_DS = 40V and I_DQ = 100mA/mm, and the base temperature was stepped from 50°C to above 200°C. Experiments of this kind allow us to examine the role of temperature in high-power degradation in a single device. We have observed a degradation pattern for I_Goff (defined @ V_GS = -5V, V_DS = 0.1V) that highly depends on stress temperature. Above a critical temperature, a sudden increase occurs (shown in Figure 1). We attribute this increase to physical defects formed along the gate edge at the drain side in the GaN cap layer. The degradation of I_Dmax (defined @ V_DS = 5V, V_GS = 2V), on the other hand, is more complex (Figure 2) and involves two different mechanisms, i.e., a trap-related degradation and a thermally activated permanent degradation. Also, I_Dmax degradation takes place only once I_Goff degradation is saturated. We have been able to extract activation energies for both I_Dmax and R_D degradation, and the two agree well. Our hypothesis for device degradation in the high-power state is that first the thin GaN cap layer is damaged, resulting in an increase in gate leakage current. Then the AlGaN barrier layer is exposed and starts getting damaged through the formation of pits. This damage leads to permanent drain current and drain resistance degradation. As the pits in the AlGaN barrier continue to grow in size, trapping effects related to such defects also increase. To verify our hypothesis, future studies will focus on the degradation behavior of devices with various cap layer thicknesses and Al compositions under the same stress conditions.

: Figure 1: Degradation of gate leakage current IGoff during high-power state stress in a step-temperature experiment from 50°C to 230°C and when the device characterization is conducted at 50°C. The numerical labels next to the data indicate the base plate temperature. A sudden increase in IGoff occurs at a base temperature stress of 170°C.

: Figure 2: Degradation of drain current and drain resistance in a step-temperature stress experiment under high-power bias. Both show thermally activated behavior. The extracted activation energies for permanent IDmax and RD degradations are 0.93 eV and 0.95 eV, respectively. The experiment setup differs from the one in Figure 1 in that two temperature ramps from 50°C to 220°C with a step of 20°C (not shown) were first carried out in order to bring IGoff degradation into saturation, and the device again was characterized at 50°C. Similar to the experiment in Figure 1, IDmax degradation occurs only after IGoff degradation is saturated.

J. A. del Alamo and J. Joh, “GaN HEMT reliability,” Microelectronics Reliability, vol. 49, pp. 1200-1206, July 2009. [↩]

Towards a Superlattice-source Nanowire FET with Steep Subthreshold Characteristics

Authors: X. Zhao, J. A. del Alamo
Sponsorship: NSF Center for Energy Efficient Electronics Science (E3S)

Achieving a sharp subthreshold swing (S) is crucial to enable the supply voltage scaling that is necessary to reducing power consumption in future logic field-effect transistors (FETs). In this research, we are investigating a new approach to accomplish this goal based on nanowire FETs with a band engineered superlattice source (SLS).

A steep S in a FET requires suppressing the subthreshold regime, which in essence is the injection of relatively high-energy source electrons above the energy barrier with the channel. A way to achieve this injection is to create a miniband in the source with a minigap above it, where no states are allowed. If the miniband is appropriately designed, no current is possible until the top of the source miniband lines up with the conduction band edge in the channel. The transition between the ON state and the OFF state can be quite sharp, and the attainable ON current can reach a value comparable to that of a regular FET. In theoretical calculations, performed by other authors^[1], it has been found that a variety of SLs can accomplish these goals: AlGaAs/GaAs, InAlAs/InGaAs, and AlGaN/GaN, among others. These are short-period SLs with barriers and wells in the 1-2 nm regime. Furthermore, 7 periods appears to be enough to accomplish the filtering action of the SL. It has also been shown that values of S in the 10-20 mV/dec are possible (at 300K).

Our goal is to demonstrate a prototype SLS NW-FET in the InAlAs/InGaAs system and to study its suitability for steep-subthreshold and ultra-low voltage operation. The proposed device is a vertical nanowire transistor with superlattice region incorporated in the source. In order to design a suitable heterostructure and device architecture, we create a simulation environment for the miniband structure of a superlattice in various material systems using Nextnano. Our calculations indicate that a demanding nanowire diameter of sub-10 nm is needed to achieve single transversal sub-band behavior.

In our quest for SLS nanowire FETs, we have developed a process to fabricate gate-all-around vertical nanowire MOSFETs, and working transistors have been demonstrated. A 30-nm InGaAs nanowire with aspect ratio of 7 is shown in Figure 1. Figure 2 shows the output characteristics of the InGaAs single-nanowire MOSFET. The gate length is 30 nm, and the nanowire diameter is 20 nm. We will continue to optimize this process for MOSFETs and simulate the transport characteristics of SLS-FETs to design a heterostructure that can maximize the energy filtering capability of SLs.

: Figure 1: A 30-nm InGaAs nanowire fabricated by our reactive ion etching process.

: Figure 2: Output characteristics of a single-nanowire MOSFET with 6 nm Al2O3 as the gate dielectric, gate length of 30 nm, and diameter of 20 nm.

E. Gnani, P. Mariorano, S. Reggiani, A. Gnudi, and G. Baccarani, “Investigation on superlattice heterostructures for steep-slope nanowire FETs,” Device Research Conference, 2011, pp. 201-202. [↩]

Towards a Self-aligned InGaAs Trigate MOSFET

Authors: A. Vardi, X. Zhao, J. A. del Alamo
Sponsorship: Sematech, NSF E3S

Si-based CMOS technology is approaching the limits of its capabilities, and as a result there is extensive research into looking for novel methods to further scale logic circuitry. III-V semiconductors are considered leading candidates for future deeply-scaled integrated technology^[1]. The low-effective mass of various III-V materials such as InGaAs and InAs gives rise to extraordinarily high electron velocities, which promise transistors with high performance at low voltage.

The fundamental requirement for future switches is simple: maximum ON current (I_ON) for a given OFF current (I_OFF) operating at a small voltage on a sub-10-nm scale. Unfortunately, there is a tradeoff between I_ON and I_OFF as the dimensions scale down. There are two approaches to address this problem. First, the material properties can be adjusted by means of strain management or alternative channel material; second, the dimensionality can be modified to obtain better electrostatic control and higher current density for a given footprint. III-V Trigate-FETs employ both approaches and are expected to show an unprecedented I_ON/I_OFF ratio at the 10-nm regime and under 0.5-V operation voltages.

This project aims to demonstrate the first self-aligned sub-10-nm InGaAs Trigate transistor. There are many challenges to overcome before III-V Trigates can be accepted as a valid alternative. Understanding how to etch high aspect ratio fins, curing etching damage, reducing the sidewalls’ interface state traps (D_it) and obtaining low access resistance are only few of the many difficulties that need to be faced. We are pursuing a device design and a process integration approach that will allow an aggressive scale-down of device dimensions. Figure 1 shows the fin- etch module test structure; we have fabricated InGaAs fins with sub-20-nm resolution using a novel RIE process. An aspect ratio as high as 10 and smooth sidewalls and surfaces have also been demonstrated (inset). Figure 2 shows the fin contacting scheme using Mo. To minimize the access resistance, the metal covers the source and drain top as well as the sidewalls.

Successful demonstration of self-aligned III-V Trigate is an important milestone of CMOS technology, which will allow Moore‘s law to be extended, safely, into the sub-10-nm regime, and we are closer than ever to making it happen.

: Figure 1: Fin etch test structures: array of 100-nm fins (pitch 200 nm). Inset: demonstration of the fin geometry that we obtain in our process; the fin is 19-nm in width and 218-nm in height.

: Figure 2. SEM image of fin contact test structure. In this device, the Mo contact covers the top as well as the fin sidewalls. The bright lines in the fin cross-section separate the cap, channel, and buffer layers.

J. A. del Alamo, “Nanometer-scale electronics with III-V compound semiconductors,” Nature, vol. 479, pp. 317-323, Nov. 2011. [↩]

Breakdown Voltage of High-voltage GaN FETs

Authors: A. Guo, J. A. del Alamo
Sponsorship: MIT-MTL GaN Energy Initiative, NDSEG Fellowship

GaN FETs offer superior advantages in high-voltage and high-temperature operation due to its large bandgap (3.4 eV) and high breakdown field strength (3.3 MV/cm). This combination of the large bandgap and high breakdown field makes these devices very attractive for power switching applications. In this regard, a key figure of merit is the breakdown voltage of the transistor, which must be high enough and stable. Most studies so far measure the breakdown voltage by driving the device to destruction, which does not allow a comprehensive study of the physics of breakdown. Our goal is to develop a benign off-state breakdown (BV_OFF) measurement scheme so that reproducible, non-destructive breakdown measurements can be obtained. These measurements will allow us to understand the physics of breakdown and suggest approaches towards the engineering of breakdown voltage of GaN FETs.

To achieve non-destructive characterizations of the off-state breakdown voltage, BV_OFF, we use the drain current injection technique proposed by our group^[1]. We inject a constant drain current (of order 1 mA/mm) while ramping the gate from above threshold to below threshold. In this way, the device is driven to breakdown by simply turning it off. During the experiment, the gate current (I_G), gate to drain voltage (V_DG) and gate to source voltage (V_DS) are recorded. Since the drain current is fixed, the device is not damaged during the measurement. Figure 1 shows an example of such measurement in a short-gate length GaN HEMT. As the device is turned off, V_DS and V_DG increase prominently, and a fraction of the current is diverted towards the gate. The fact that this transfer is not complete suggests that breakdown is limited by a channel mechanism such as punchthrough or impact ionization. In devices with gate lengths of 2.5 um or above, we have observed drain to gate breakdown as the injected drain current completely went through the gate when the device was turned off. During our measurements, we have found that severe trapping occurs. This limits their repeatability. We can successfully mitigate the trapping limitation through a high temperature bake (200°C for 10 minutes) performed after each measurement. This treatment yields reproducible measurements of the breakdown voltage. Systematic characterization of the breakdown voltage has allowed us to study the geometrical dependence of BV_OFF on gate length and gate-to-drain spacing, as shown in Figure 2.

Next, we will study the temperature dependence of breakdown voltage in GaN HEMTs, in our effort to understand the physics of BV_OFF. We will also study how the breakdown mechanism changes with device geometry and current level and investigate the role of trapping in the breakdown voltage measurements.

: Figure 1: Breakdown voltage measurement using the drain current injection technique (ID = 1 mA/mm). The inset shows the circuit diagram of this technique. As the device is turned off, we observe the onset of channel breakdown before gate breakdown. This phenomenon is typical for short-channel devices.

: Figure 2: Drain to source off-state breakdown voltage (BVDS) as a function of gate length and gate to drain gap. BVDS increases with LG and saturate at long LG. BVDS also increases with the gate to drain gap length.

S. R. Bahl and J. A. del Alamo, “A new drain-current injection technique for the measurement of off-state breakdown voltage in FETs,” Electron Devices, IEEE Transactions on, vol. 40, no. 8, pp. 1558,1560, Aug. 1993. [↩]

A Ballistic Transport Model for III-V HEMTs and MOSFETs

Authors: S. Warnock, J. A. del Alamo
Sponsorship: SRC/FCRP MSD

As silicon metal-oxide-semiconductor field-effect transistors (MOSFETs) keep scaling down in size, fundamental physical limits threaten the continued improvement on their logic performance. With silicon approaching these limits, MOSFETs designed with III-V semiconductors have emerged as promising candidates to replace them. The low-effective mass of various III-V materials such as InGaAs and InAs allow both faster and more power efficient performance^[1]. However, one of the key challenges, particularly as devices continue to shrink, is to understand the importance of non-idealities in field-effect transistor (FET) structures. High-electron-mobility transistors (HEMTs) are III-V quantum-well FETs that can be used to explore many issues of relevance to future III-V MOSFETs. HEMTs are worthwhile transistors in their own right, but they are also simpler than III-V MOSFETs and therefore allow a more thorough exploration into the basic transport physics of a quantum-well III-V device.

HEMT experimental data show that electrons travel ballistically at gate lengths of 30-40 nm, suggesting that a ballistic transport model will become only more accurate as channel lengths are scaled down to 10 nm. We investigate to what extent this is true in III-V MOSFETs and also study the impact of short channel effects and other parasitics inherent in a III-V design.

To accomplish these goals, we have developed a flexible transistor model in MATLAB based on a ballistic theory of transport. The model uses, at its core, a one-dimensional, self-consistent Poisson-Schrödinger simulation of the heterostructure of the transistor. We then add extrinsic device parameters such as source and drain parasitic resistances (R_S and R_D), as well as appropriate values for the drain-induced barrier lowering (DIBL) and a distribution of interface trap states across the band gap at the semiconductor-oxide interface (D_it). We first used HEMTs to calibrate the model’s validity with regards to the current-voltage characteristics. Due to the absence of a gate oxide, HEMTs do not suffer from interface states. We then turned to the physics of relevance to III-V MOSFETs, particularly the effects of D_it on the C-V and I-V characteristics. We can use our model to extract trap density as a function of energy in the bandgap of the barrier semiconductor. Figure 1 shows the C-V curves for a simulated MOSFET structure first with no D_it, and then fitted to an experimental C-V curve using the D_it distribution shown in Figure 2. The MOSFET used for this comparison is an Al₂O₃ buried-channel device fabricated by Lin et al. and described in^[2]. Ultimately, the ability to correctly model and predict device behavior will help identify the problems that need attention in the iterations of future device fabrication.

: Figure 1: C-V characteristics of model simulation against experimental data for the long-channel Al2O3 III-V MOSFET in [2], at room temperature. The threshold voltage was fit with I-V sub-threshold characteristics.

: Figure 2. Dit distribution for III-V MOSFET in [2], extracted from C-V characteristics in Figure 1. The Dit distribution is inside the band gap of the InP barrier layer.

J. A. del Alamo, “Nanometer-scale electronics with III-V compound semiconductors,” Nature, vol. 479, pp. 317-323, Nov. 2011. [↩]
J. Lin, D. A. Antoniadis, and J. A. del Alamo, “Sub-30 nm InAs Quantum-Well MOSFETs with Self-aligned Metal Contacts and Sub-1 nm EOT HfO2 Insulator,” IEEE International Electron Devices Meeting, San Francisco, CA, Dec. 10-12, 2012, pp. 757-760. [↩]

Nano-scale Metal Contacts for III-V FETs

Authors: W. Lu, J. A. del Alamo
Sponsorship: SRC/FCRP MSD, Intel

In the last few years, III-V compound semiconductors have emerged as a promising family of materials to replace silicon in logic applications^[1]. Novel III-V MOSFET prototypes with superior electron-transport properties have been recently demonstrated^[2]. One of the challenges to obtain high performance is to achieve a very low ohmic contact resistance. As transistor scaling continues, it is important to fabricate and characterize high-quality ohmic contacts with nanometer-scale contact length. In this project, a nano-scale transmission line model (nano-TLM) structure is being developed to study and optimize metal contacts for III-V field-effect transistors.

This works builds on prior research in our group on the fabrication and characterization of nanoscale contacts to III-V FET structures^[3]. Our nano-TLM structure comprises a Mo contact on an InGaAs heterostructure, with various contact lengths (L_c) and spacings (L_d). The Mo contact is patterned by electron beam lithography, followed by reactive-ion etching (RIE). The mesa isolation and contact pads are fabricated by a series of lithography, RIE, and lift-off processes. The ohmic contact is annealed at 400 °C for 40 s. Figure 1 shows a nano-TLM with L_c= 19 nm, the smallest contacts we have fabricated at present. The finished test structures are characterized using Kelvin 4-terminal measurement. We developed a 2-D circuit model to extract the contact resistivity, semiconductor sheet resistance, and metal sheet resistance. Figure 2 shows resistance measurements on Mo-n⁺-InGaAs structures with 80-nm contact length and various contact spacings. From measurements of this kind in several structures, an average contact resistivity of 0.6 Ω∙μm² is obtained.

Our research will continue to optimize the contact fabrication to achieve lower contact resistance and further scaling. We will also investigate the contact resistance to a buried channel. We will further explore metals contacts on p-type Sb-based heterostructures, which are as critical as the n-type counterpart but in great need of a high-quality ohmic contact.

: Figure 1: SEM image showing the top view of a Mo-n+-InGaAs nano-TLM structure, with contact length Lc = 19 nm. The inset is a close view of Mo contacts at the edge of the mesa.

: Figure 2: Experimental nano-TLM resistance of test structures with average contact length of 80 nm. The values of ρc, Rsh, and Rshm are extracted by the 2D nano-TLM model. The insets show the two configurations in the Kelvin measurements.

J. A. del Alamo, “Nanometre-scale electronics with III-V compound semiconductors,” Nature, vol. 479, no. 7373, pp. 317-323, Nov. 2011. [↩]
J. Lin, D. A. Antoniadis, and J. A. del Alamo, “Sub-30 nm InAs quantum-well MOSFETs with self-aligned metal contacts and sub-1 nm EOT HfO2 insulator.” IEEE International Electron Devices Meeting, San Francisco, CA, December 10-12, 2012, pp. 757-760. [↩]
A. Guo and J. A. del Alamo, “Mo/n⁺-InGaAs nanocontacts for future III-V MOSFETs,” 25^th International Conference on Indium Phosphide and Related Materials, Kobe, Japan, May 19-23, 2013. [↩]

Enhancement of Antimonide-based P-channel FETs using Process-induced Strain

Authors: L. W. Guo, L. Xia, B. R. Bennett, J. B. Boos, M. G. Ancona, J. A. del Alamo
Sponsorship: Intel, Focus Center Research Program, NSF GRFP

For decades, growth and innovation in the microelectronics industry has been fueled by the aggressive scaling of silicon complementary metal oxide semiconductor (CMOS) technology. However, as silicon devices scale to the nanometer regime and their intrinsic limitations become more pronounced, the role of silicon in state-of-the-art logic devices is being called into question. Consequently, III-V semiconductors have gathered great interest as a channel material to replace silicon, largely due to their impressive electron transport properties and the successful demonstration of outstanding n-channel devices^[1]. On the other hand, this success has not yet been translated to III-V p-channel devices because of the low intrinsic hole mobilities of most III-V semiconductors. Developing a high performance p-channel device is critical to the realization of a future III-V CMOS architecture to extend the semiconductor roadmap and enable future novel semiconductor technologies.

A promising solution to the III-V p-channel problem is the use of antimonides, which have the largest hole mobilities of any III-V material system. The performance of antimonide devices can be further enhanced by strain, which has already found great success in high-volume silicon manufacturing. Chip-bending experiments using antimonide p-channel FETs have shown that antimonides respond favorably to strain^[2]. In this work, we show that the performance of p-channel antimonide FETs can be further enhanced using a compressively stressed nitride layer^[3].

Compressively stressed p-channel FETs with a 0.5-μm gate length were fabricated using a 7.5-nm In_0.41Ga_0.59Sb channel. Figures 1 and 2 show, respectively, the output characteristics and transconductance g_m of a typical transistor. A peak g_m of 115 mS/mm was obtained, comparable to similarly fabricated unstressed devices with a gate length of 0.25 μm, despite having a gate length twice as long. This peak gives strong evidence for stress-induced transport enhancement.

Ongoing work includes efforts to fabricate shorter-channel transistors to capture even more stress enhancement, as simulations project the gains from stress to increase with gate length scaling.

: Figure 1: Output characteristics of In0.41Ga0.59Sb pFET with Lg = 0.5 μm fabricated with a stressed nitride layer. The device shows good saturation characteristics. The large gate leakage is under investigation.

: Figure 2: Transconductance of Lg = 0.5 μm device with a stressed nitride layer. A peak transconductance, gm, of 115 mS/mm was obtained.

J. A. del Alamo, “Nanometer-scale electronics with III-V compound semiconductors,” Nature, vol. 479, no.7373, pp. 317-323, Nov. 2011. [↩]
L. Xia, J. B. Boos, B. R. Bennett, M. G. Ancona, and J. A. del Alamo, “Hole mobility enhancement in In_0.41Ga_0.59Sb quantum-well field effect transistors,” Applied Physics Letters, vol. 98, no 5, 053505, Feb. 2011. [↩]
L. Xia, V. Tokranov, S. R. Oktyabrsky, and J. A. del Alamo, “Performance enhancement of p-channel InGaAs quantum-well FETs by superposition of process-induced uniaxial strain and epitaxially-grown biaxial strain,” in IEDM ’11 Technical Digest, pp. 315-318, Dec. 2011. [↩]

Reliability of GaN MIS-HEMTs for Power-switching Applications

Authors: D. Jin, J. A. del Alamo
Sponsorship: ARPA-E, SRC, DRIFT-MURI

Engineering energy-efficient power electronic systems has recently attracted tremendous interest. Similarly, the gallium nitride metal-insulator-semiconductor high-electron-mobility transistor (GaN MIS-HEMT) fabricated on large diameter Si substrates has emerged as a commercially viable technology promising both low price and better than three orders of magnitude improvement in the ON-resistance (R_ON)/breakdown-voltage trade-off over state-of-the-art Si power-switching devices. However, its unknown electrical reliability hampers wide deployment of this technology. A particularly critical concern is the dynamic ON resistance (R_ON)^[1],^[2], in which the R_ON of the transistor substantially increases and remains high for a time after an OFF-ON switching event. This anomaly significantly reduces the total efficiency in a power management circuit system.

Figure 1 shows an example of the evolution of R_ON in GaN-on-Si MIS-HEMTs designed for high-voltage operation of more than 600 V in an OFF-state step-stress-recovery experiment. Here, a 150-sec OFF-state stress period is followed by a 150-sec recovery period at rest (V_DS=V_GS=0 V). The sample is in the dark, and R_ON has been continuously characterized every 10 sec. For each stress period, V_GS= -12 V and V_DS is increased from 50 V to 600 V in 50 V steps. During the stress periods, R_ON substantially increases as V_DS increases from 250 V to 600 V and in the following recovery periods, it slowly decreases to the initial value. Additional UV light illumination experiments on this sample prove that the increase in dynamic R_ON is fully recoverable up to 600 V. The observed behavior suggests that heavy electron trapping takes place in the device as a result of the applied high voltage under OFF-state operation. This eventually deteriorates the energy efficiency of the entire power system.

Figure 2 shows all four terminal leakage currents during the stress periods. In these MIS-HEMTs, the dominant breakdown leakage current appears to flow from the drain to the substrate. No degradation in the gate leakage current is observed. This finding suggests that the gate leakage current is less relevant for the R_ON increase in Figure 1. However, engineering the high resistive buffer and Si substrate to reduce vertical leakage current becomes very important in achieving higher breakdown-voltage as well as suppression of any related trapping effects. For a GaN-on-Si MIS-HEMT high-frequency power switching technology to become commercial, the dynamic R_ON phenomena should be well understood and ultimately resolved down to times in the sub-µs range.

: Figure 1: Time evolution of RON/RON(0) in the OFF-state step-stress-recovery experiment in GaN MIS-HEMTs. VDS is step-stressed from 50 V to 600 V in 50 V steps and 150-sec stress periods. A 150-sec recovery period follows each stress period. Electron trapping during the high-voltage OFF-state operation induces significant but slowly recoverable RON degradation.

: Figure 2: Time evolution of source (IS), gate (IG), drain (ID), substrate (IB) leakage currents in the stress periods of Figure 1. As the OFF-state bias increases, the drain-to-substrate leakage current also increases with a minor increase in the source current. The gate leakage current is stable, presumably due to the robust MIS structure and field plate engineering.

D. Jin and J. A. del Alamo, “Mechanisms responsible for dynamic on-resistance in GaN high-voltage HEMTs,” Power Semiconductor Devices and ICs (ISPSD), 2012 24^th International Symposium on, pp. 333-336, Jun. 2012. [↩]
D. Jin and J. A. del Alamo, “Impact of high-power stress on dynamic ON-resistance of high-voltage GaN HEMTs,” Microelectron. Reliab., vol. 52, no. 12, pp. 2875-2879, Dec. 2012. [↩]

MTL Annual Research Report 2013