Towards a Superlattice-source Nanowire FET with Steep Subthreshold Characteristics
- Category: Electronic Devices, Materials, Nanotechnology
- Tags: jesus del alamo, xin zhao
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Download as PDFAchieving a sharp subthreshold swing (S) is crucial to enable the supply voltage scaling that is necessary to reducing power consumption in future logic field-effect transistors (FETs). In this research, we are investigating a new approach to accomplish this goal based on nanowire FETs with a band engineered superlattice source (SLS).
A steep S in a FET requires suppressing the subthreshold regime, which in essence is the injection of relatively high-energy source electrons above the energy barrier with the channel. A way to achieve this injection is to create a miniband in the source with a minigap above it, where no states are allowed. If the miniband is appropriately designed, no current is possible until the top of the source miniband lines up with the conduction band edge in the channel. The transition between the ON state and the OFF state can be quite sharp, and the attainable ON current can reach a value comparable to that of a regular FET. In theoretical calculations, performed by other authors[1], it has been found that a variety of SLs can accomplish these goals: AlGaAs/GaAs, InAlAs/InGaAs, and AlGaN/GaN, among others. These are short-period SLs with barriers and wells in the 1-2 nm regime. Furthermore, 7 periods appears to be enough to accomplish the filtering action of the SL. It has also been shown that values of S in the 10-20 mV/dec are possible (at 300K).
Our goal is to demonstrate a prototype SLS NW-FET in the InAlAs/InGaAs system and to study its suitability for steep-subthreshold and ultra-low voltage operation. The proposed device is a vertical nanowire transistor with superlattice region incorporated in the source. In order to design a suitable heterostructure and device architecture, we create a simulation environment for the miniband structure of a superlattice in various material systems using Nextnano. Our calculations indicate that a demanding nanowire diameter of sub-10 nm is needed to achieve single transversal sub-band behavior.
In our quest for SLS nanowire FETs, we have developed a process to fabricate gate-all-around vertical nanowire MOSFETs, and working transistors have been demonstrated. A 30-nm InGaAs nanowire with aspect ratio of 7 is shown in Figure 1. Figure 2 shows the output characteristics of the InGaAs single-nanowire MOSFET. The gate length is 30 nm, and the nanowire diameter is 20 nm. We will continue to optimize this process for MOSFETs and simulate the transport characteristics of SLS-FETs to design a heterostructure that can maximize the energy filtering capability of SLs.
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- Figure 1: A 30-nm InGaAs nanowire fabricated by our reactive ion etching process.
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- Figure 2: Output characteristics of a single-nanowire MOSFET with 6 nm Al2O3 as the gate dielectric, gate length of 30 nm, and diameter of 20 nm.
- E. Gnani, P. Mariorano, S. Reggiani, A. Gnudi, and G. Baccarani, “Investigation on superlattice heterostructures for steep-slope nanowire FETs,” Device Research Conference, 2011, pp. 201-202. [↩]