All entries for Tomas Palacios

• Print This Page
• Download as PDF

GaN High Frequency Transistors

• Authors: D. S. Lee, X. Gao, S. Guo, T. Palacios
• Sponsorship: DARPA NEXT, NSF CAREER Award, ONR DURIP

GaN-based high electron mobility transistors (HEMTs) have great potential for high power/frequency applications due to their outstanding combination of large breakdown voltage and high electron velocity. Among the different possible nitride structures, InAlN/GaN heterostructures have attracted much attention recently because they enable an extremely high charge density with a thin barrier thickness ^[1] . With the use of these advantages, outstanding progress in the frequency performance of InAlN/GaN transistors has been recently achieved. Sun et al. reported a 55-nm gate length device with f_T of 205 GHz (f_max = 191 GHz) ^[2] and Lee et al. demonstrated a 30-nm gate length device with f_T of 245 GHz ^[3] .

In this study, we used an AlGaN back-barrier in InAlN/GaN HEMT structures for the first time and studied its impact on the DC and RF characteristics of these devices ^[4] . A maximum drain current of 1.49 A/mm is obtained at V_gs=2 V in the device with the back-barrier, about 27 % lower than that of the standard device (2.05 A/mm at V_gs=2 V). The smaller drain current in the device with the back-barrier mainly results from the lower sheet charge density and subsequent higher threshold voltage. However, the output conductance is significantly smaller in the device with the back-barrier, which shows an effective suppression of the  short-channel effects. In addition, in sub-100-nm-gate-length transistors, the back-barrier makes it possible to maintain a drain-induced barrier lowering (DIBL) near 50-60 mV/V while preventing the degradation of the subthreshold swing (SS). Thanks to the reduced short-channel effects, 65-nm-gate-length devices with a back-barrier showed an f_T of 210 GHz, which is higher than that of the standard device with the same gate length (195 GHz). Moreover, in a sub-30-nm-gate-length device with AlGaN back-barrier, an f_T of 270 GHz, the highest f_T ever reported in GaN transistors, was achieved.



Figure 1: Output characteristics of InAlN/GaN HEMTs (L_g = 65-nm) with and without an AlGaN back-barrier.



Figure 2: RF performance of the 65-nm-gate-length InAlN/GaN HEMTs (a) with and (b) without the AlGaN back-barrier.




1. J. Kuzmik, “Power electronics on InAlN/(In)GaN: Prospect for a record performance,” IEEE Electron Device Lett. vol. 22, no. 11, pp. 510-512, Nov. 2001. [↩]
2. H. Sun, A. R. Alt, H. Benedickter, E. Feltin, J.-F. Carlin, M. Gonschorek, N. Grandjean, and C. R. Bolognesi, “205-GHz (Al, In)N/GaN HEMTs,” IEEE Electron Device Lett., vol. 31, no. 9, pp. 957-959, Sep. 2010. [↩]
3. D. S. Lee, J. W. Chung, H. Wang, X. Gao, S. Guo, P. Fay, and T. Palacios, “245 GHz InAlN/GaN HEMTs with oxygen plasma treatment,”  IEEE Electron Device Lett., vol. 32, no.6, pp.755-757, Jun. 2011. [↩]
4. D. Lee, X. Gao, S. Guo, and T. Palacios, “InAlN/GaN HEMTs with AlGaN back-barriers,” IEEE Electron Device Lett., vol. 32, no. 5, pp.-617-619, May 2011. [↩]

MIT-MTL Center for Graphene Devices and Systems

• Leadership: Professor Tomas Palacios, Director

The MIT/MTL Center for Graphene Devices and Systems (MIT-CG) brings together, MIT researchers and industrial partners to advance the science and engineering of graphene-based technologies.

The center explores advanced technologies and strategies that enable graphene-based materials, devices and systems to provide discriminating or break-through capabilities for a variety of system applications ranging from energy generation and smart fabrics and materials, to RF communications and sensing.  The MIT-CG  supports the development of the science, technology, tools and analysis for the creation of a vision for the future of graphene-enabled systems.

Membership privileges for MIT-CG include:

Stay abreast of research developments in graphene
•  Webcast of seminars
•  Complimentary attendance to meetings
•  Facilitated access to IP
Interact with students and faculty at MIT-GC events
•  Industry Focus Day
•  Resume book of graduating students
Participate in working groups of leading companies and researchers in defining the path forward for graphene
•  Timely white papers on key issues
Collaborate with leading researchers on research that addresses today’s challenges
•  Direct student projects on modeling in support of working group activities
•  Pre-competitive teaming

Tomás Palacios

• Title: Emmanuel E. Landsman CD Associate Professor
• Department: Department of Electrical Engineering and Computer Science

Collaborators

• D. Antoniadis, MIT
• J. del Alamo, MIT
• P. Jarillo-Herrero, MIT
• D. Jena, University of Notre Dame
• J. Kong, MIT
• U. K. Mishra, University of California – Santa Barbara
• E. Monroy, CEA-Grenoble, France
• E. Munoz, ETSIT-UPM, Spain
• D. Perreault, MIT
• C. Thompson, MIT
• H. Xing, University of Notre Dame

Visiting Scientists

• M. Azize, Post Doc, France
• H.-S. Lee, Post Doc, South Korea
• E. Matioli, Post Doc, Brazil

Graduate Students

• F. Gao, Res. Asst.
• A. Hsu, Res. Asst.
• D. S. Lee, Res. Asst.
• B. Lu, Res. Asst.
• B. Mailly, Res. Asst.
• M. Medlock, Res. Asst.
• D. Piedra, Res. Asst.
• O. I. Saadat, Res. Asst.
• M. Sun, Res. Asst.
• H. Wang, Res. Asst.
• X. Zhang, Res. Asst.

Undergraduate Student

• B. Jain

Support Staff

• E. Kubicki, Admin. Asst. II

Publications

Chung, J.W., W. E. Hoke, E. M. Chumbes, and T. Palacios, “AlGaN/GaN HEMT with 300-GHz f_max,” Electron Dev. Letts., vol. 31, pp. 195-197, 2010.

Lu, B., E. L. Piner, and T. Palacios, “Schottky Drain Technology for High Voltage AlGaN/GaN HEMTs on Si Substrates,” Electron Dev. Letts., vol. 31, pp. 302-304, 2010.

Wang, H., J. W. Chung, X. Gao, S. Guo, and T. Palacios, “Al₂O₃ Passivated InAlN/GaN HEMTs on SiC Substrate with Record Current Density and Transconductance,” Physica Status Solidi (c), vol. 7, pp. 2440-2444, 2010.

Palacios, T., A. Hsu, and H. Wang, “Applications of Graphene Devices in RF Communications,” IEEE Communications Magazine, vol. 48, pp. 122-128, 2010 (Invited).

Simms, R. J. T., F. Gao, Y. Pei, T. Palacios, U. K. Mishra, and M. Kuball, “Electric Field Distribution in AlGaN/GaN HEMTs Investigated by Electroluminescence,” Appl. Phys. Letts., vol. 97, 033502, 2010.

Joh, J., F. Gao, T. Palacios, and J. A. del Alamo, “A model for the critical voltage for electrical degradation of GaN high electron mobility transistors,” Microelectronics Reliability, vol. 50, pp. 676-773, 2010.

Wang, H., A. Hsu, J. Wu, J. Kong, and T. Palacios, “Graphene-based Ambipolar RF Mixers,” Electron Dev. Letts., vol. 31, pp. 906-908, 2010.

Azize, M., and T. Palacios, “Effect of substrate-induced strain in the transport properties of AlGaN/GaN heterostructures,” J. of Appl. Phys., vol. 108,  023707, 2010.

Makaram, P., J. Joh, J. del Alamo, T. Palacios, and C. V. Thompson, “Evolution of Structural Defects Associated with Electrical Degradation in AlGaN/GaN HEMTs,” Appl. Phys. Letts, vol. 96, 233509, 2010.

Lu, B. and T. Palacios, “High Breakdown (>1500 V) AlGaN/GaN HEMTs by Substrate-Transfer Technology,” Electron Dev. Letts., vol. 31, pp. 951-953, 2010.

Lu, B., O. I. Saadat and T. Palacios, “High-Performance Integrated Dual-Gate AlGaN/GaN Enhancement-Mode Transistor,” Electron Dev. Letts., vol. 31, pp. 990-992, 2010.

Tirado, J. M., D. Nezich, X. Zhao, J. W. Chung, J. Kong, and T. Palacios, “Study of Transport Properties in Graphene Monolayer Flakes on SiO₂ Substrates,” J. Vac. Sci. Technol. B, vol. 28 (6), pp. C6D11-14, 2010.

Palacios, T., “Graphene Ambipolar Electronics,” Recent Advances in Graphene and Related Materials, Singapore, 1-6 August 2010. (Invited)

Palacios, T., “GaN Transistors: Revolutionizing Electronics from Terahertz to Kilovolts,” International Workshop on Nitride Semiconductors (IWN-2010), Tampa, FL, 19-24 September 2010. (Invited, Plenary)

Palacios, T., “Future of GaN Electronics,” European Microwave Week, CNIT, Paris, France, 26 September – 1 October 2010. (Invited)

Ryu, K., J. W. Chung, B. Lu, and T. Palacios, “Wafer Bonding Technology in Nitride Semiconductors for Applications in Energy and Communications,” 218th Meeting of the Electrochemical Society, Las Vegas, NV, 11-15 October 2010. (Invited)

Wang, H. A. Hsu, K. Kang Kim, J. Kong, and T. Palacios, “Gigahertz Ambipolar Frequency Multipliers based on CVD Graphene,” Proc. Of the International Electron Device Meeting, pp. 572-575, San Francisco, CA (2010).

Chung, J. W., T.-W. Kim, and T. Palacios, “Advanced Gate Technologies for State-of-the-art f_T in AlGaN/GaN HEMTs,” Proc. Of the International Electron Device Meeting, pp. 676-679, San Francisco, CA (2010).

High-speed Graphene Circuits and Photodetectors

• Authors: A. Hsu, H. Wang, K. K. Kim, J. Kong, T. Palacios
• Sponsorship: ONR Gate MURI, MSD Focus Center, Institute of Soldier Nanotechnology

The most common substrate for processing chemical vapor deposition (CVD) graphene and highly oriented pyrolytic graphite (HOPG) has been thermally grown silicon dioxide on top of silicon. Due to optical interference, monolayer and bilayers of graphene can be easily identified using a standard optical microscope ^[1] . Furthermore, graphene is capacitively coupled to the underlying silicon, allowing for rapid electrical characterization through substrate biasing. While this substrate has proven useful for probing carrier transport in graphene as well as for developing graphene processing technology, the parasitic capacitances associated with the underlying silicon limit high-frequency performance. In this work, we have explored fabrication of graphene on purely insulating substrates, specifically sapphire. Sapphire is a common substrate used for radio frequency (RF) applications due to its low conductivity. Furthermore, it is much cheaper than other insulating substrates such as SiC or diamond.

Through recent advances in improved ohmic processing using an oxidized aluminum capping layer, we are able to fabricate high-speed field effect transistors on both silicon dioxide and sapphire ^[2] . Figure 1 shows measured RF data for a device with gate length (L_g) = 2 µm and width (W) = 25 µm on each substrate. While RF performance of graphene on silicon is slightly better after de-embedding than that of the sample on sapphire, we attribute this discrepancy to non-optimized processing conditions, possibly due to the transfer anneal or fabrication problems on transparent substrates. Fortunately, we are still able to achieve an extrinsic f_t-L_g product of 14 GHz-µm on sapphire, which to our best knowledge is the highest reported extrinsic value on CVD graphene (Figure 2 ^{[3] [4] [5] [6] [7] [8]} ). In parallel, scanning photocurrent measurements of graphene on silicon dioxide show optical sensitivities of 0.4 mA/W for large-area devices (>375 µm²). Therefore, combining our results on sapphire with optical measurements should hopefully allow for large-area arrays of high-speed graphene photodetectors.



Figure 1: RF performance between graphene on (a) 300-nm SiO2/Si and (b) sapphire. Values shown are extrinsic ft and de-embedded ft.



Figure 2: Comparison of RF performance from devices from literature as well as silicon ^{[3] [4] [5] [6] [7] [8]} . Red symbols represent extrinsic performance (f_t,ext); blue symbols are values after de-embedding (f_t,deebmed). The dotted line is the performance of 90-nm SOI NMOS reported in ^[8] .




1. X. Wang, M. Zhao, and D. D. Nolte, “Optical contrast and clarity of graphene on an arbitrary substrate,” Applied Physics Letters, vol. 95, p. 081102, 2009. [↩]
2. A. Hsu, H. Wang, K. K. Kim, J. Kong, and T. Palacios, “Impact of graphene interface quality on contact resistance and RF device performance,” submitted for publication. [↩]
3. J. S. Moon, D. Curtis, M. Hu, D. Wong, C. McGuire, P. M. Campbell, G. Jernigan, J. L. Tedesco, B. VanMil, R. Myers-Ward, C. Eddy, Jr., and D. K. Gaskill, “Epitaxial-graphene RF field-effect transistors on Si-face 6H-SiC substrates,” Electron Device Letters, vol. 30, pp. 650, 2009. [↩] [↩]
4. Y. Wu, Y. Lin, A. A. Bol, K. A. Jenkins, F. Xia, D. B. Farmer, Y. Zhu, and P. Avouris, “High-frequency, scaled graphene transistors on diamond-like carbon,” Nature, vol. 472, p. 74, 2011. [↩] [↩]
5. Y. Lin, C. Dimitrakopoulos, K.A. Jenkins, D. B. Farmer, H.Y. Chiu, A. Grill and P. Avouris, “100-GHz Transistors from wafer-scale epitaxial graphene,” Science vol. 327, p. 662, 2010. [↩] [↩]
6. Y. Lin, K. A. Jenkins, A. Valdes-Garcia, J. P. Small, D. B. Farmer and P. Avouris, “Operation of graphene transistors at gigahertz frequencies,” Nano Lett., vol. 9, p. 422, 2009. [↩] [↩]
7. L. Liao, Y. C. Lin, M. Bao, R. Cheng, J. Bai, Y. Liu, Y. Qu, K. L. Wang, Y. Huang, and X. Duan, “High-speed graphene transistors with a self-aligned nanowire gate,” Nature, vol. 467, p. 305, 2010. [↩] [↩]
8. J. Plouchart, J. Kim, J. Gross, R. Trzcinski, and K. Wu, “Scalability of SOI CMOS technology and circuit to millimeter-wave performance,” presented at CSIC Symposium 2005. [↩] [↩] [↩]

Compact Physical Modeling of Graphene Field Effect Transistors

• Authors: H. Wang, A. Hsu, J. Kong, D. A. Antoniadis, T. Palacios
• Sponsorship: SRC/FCRP MSD, ONR GATE MURI Program

Graphene is a two-dimensional (2D) material that has attracted great interest for electronic devices since the demonstration of field effect carrier modulation in 2004 ^[1] . Its high mobility and high saturation velocity make graphene a promising material for next generation of high-frequency devices ^[2] , and its 2D geometry also makes it highly compatible with existing fabrication technology in the semiconductor industry. Furthermore, the possibility of large-scale synthesis of graphene by chemical vapor deposition (CVD) and epitaxial growth ^{[3] [4] [5]} makes graphene integrated circuits a feasible reality in the near future. Hence, it is desirable to develop a compact physical model that can enable the use of computer-aided-design software to simulate future complex circuits. In this work, we develop a compact model for the current-voltage characteristics of graphene field effect transistors (GFETs), which is based on an extension of the “virtual-source” model previously proposed for Si MOSFETs ^{[6] [7]} and is valid for both saturation and non-saturation regions of device operation (Figure 1). This virtual source model provides a simple and intuitive understanding of carrier transport in GFETs, allowing extraction of the virtual source injection velocity v_VS, a physical parameter with great technological significance for short-channel graphene transistors. With only a small set of fitting parameters, the model shows excellent agreement with experimental data (Figure 2). It is also shown that the extracted virtual source carrier injection velocity for graphene devices is much higher than in Si MOSFETs and state-of-the-art III-V HFETs with similar gate length, supporting the great potential of GFETs for high frequency applications. Future work includes extending the model for both small signal and large signal modeling of GFETs RF performance and implementation in Verilog to enable modeling of graphene circuits.



Figure 1: Schematic diagram of the cross-section of a GFET device. The virtual electron source (VES) point and the virtual hole source (VHS) point in the channel are defined for a GFET. The electrostatic potential along the channel and the position of VES and VHS are shown for a GFET operating in the three operating regions: I. Electron conduction region; II. Ambipolar region; III. Hole conduction region.



Figure 2: (a) Top-view of the three-dimensional plot of I_DS vs. V_TGS and V_BGS at V_DS=1.1 V. (b), (c) and (d) are cross-sections in (a) at the corresponding dotted lines. The model results are shown as solid lines; the experiment data is shown as dots. In (b), V_BGS is kept constant at 0 V, and V_TGS is swept from -1 V to 3 V. A family of curves is shown for VDS increasing from 0.35 V to 1.1 V in steps of 0.25 V. In (c), V_TGS is kept constant at 0 V, and V_BGS is swept from -50 V to 100 V. (d) V_TGS is kept constant at 1.41 V, and V_BGS is swept from -30 V to 40 V. A family of curves is shown for V_DS, increasing from 0.35 V to 1.1 V in steps of 0.25 V.




1. K. S. Novoselov, et al., “Electric field effect in atomically thin carbon films,” Science, vol. 306, pp. 666-669, Oct. 2004. [↩]
2. T. Palacios, et al. “Applications of graphene devices in RF communications,” IEEE Comm. Mag., vol. 48,  no. 6, pp. 122-128, June 2010. [↩]
3. A. Reina, et al., “Large area few-layer graphene films on arbitrary substrates by Chemical Vapor Deposition,” Nano Lett., vol. 9, no. 1, pp. 30-35, Jan. 2009. [↩]
4. X. Li, et al. “Large-area synthesis of high-quality and uniform graphene films on copper foils,” Science, vol. 324. no. 5932, June 2009. [↩]
5. C. Berger, et al. “Electronic confinement and coherence in patterned epitaxial graphene,” Science, vol. 312. no. 5777, May 2006. [↩]
6. A. Khakifirooz, O. M. Nayfeh, and D. Antoniadis “A simple semiempirical short-channel MOSFET current-voltage model dontinuous across all regions of operation and employing only physical parameters,” IEEE Trans. Electron Devices, vol. 56, no. 8, Aug. 2009. [↩]
7. D. A. Antoniadis, I. Åberg, C. N. Chleirigh, O. M. Nayfeh, A. Khakifirooz, and J. L. Hoyt, “Continuous MOSFET performance increase with device scaling: The role of strain and channel material innovation,” IBM J. Res. Develop., vol. 50, no. 4/5, pp. 363–376, July 2006. [↩]

Graphene Ambipolar Electronics for RF Applications

• Authors: H. Wang, A. Hsu, J. Kong, K. K. Kim, T. Palacios
• Sponsorship: ONR GATE MURI Program, Institute for Soldier Nanotechnologies

Graphene is a one-atom-thick layer of carbon atoms arranged in a honeycomb lattice through sp² bonding ^[1] . Considered for many years an impossible goal, the isolation of graphene triggered a revolution not only among condensed-matter physicists but also among chemists and engineers, eager to take advantage of its unique properties ^[2] . The symmetry of its honeycomb lattice structure confers to graphene very unique transport properties ^[3] . For example, the carriers in graphene lose their effective mass and can be described by a Dirac-like equation instead of by the Schrödinger equation used in traditional semiconductors. This very low effective mass is responsible for a very high electron and hole mobility in excess of 100,000 cm²/Vs at room temperature ^[4] , the highest ever reported for any semiconductor. In this work, we develop novel graphene electronic devices using graphene grown by chemical vapor deposition. These new applications of graphene rely on its ambipolar transport properties to provide unique device level functionalities, which can significantly simplify the designs of many basic RF circuit blocks, such as frequency multipliers and mixers ^{[5] [6]} . The new graphene ambipolar frequency multipliers, integrated on a sapphire substrate, can operate at 16 GHz with extremely high output spectral purity (> 90%) (Figure 1) and are the fastest circuit level demonstration ever made using graphene. These Ku-band graphene frequency multipliers, made from wafer-scale graphene synthesis and fabrication processes, show the great potential of graphene-based ambipolar devices for RF and mixed-signal applications. Other applications such as graphene ambipolar mixers (Figure 2) can suppress odd order intermodulations more effectively than in traditional unipolar FET mixers [6]. These graphene devices have great potential for applications in future high performance transparent and flexible electronics.



Figure 1: (a) Experimental demonstration of frequency doubling measured by an Agilent DSA90604A oscilloscope. The input is at 3 GHz. The output fundamental frequency is 6 GHz. (b) Power spectrum of the output signal from the graphene frequency doublers. The input is at 8 GHz. Frequency doubling is clearly visible. The signal power at f_out=2f_in=16 GHz is about 10 dB higher than signal power at f_out= f_in=8 GHz without filtering. More than 90% of the total RF power in the output signal is at 16 GHz. All data are obtained using Agilent N9010A spectrum analyzer.



Figure 2: (a) Demonstration circuit of graphene ambipolar mixers. (b) Spectrum analysis: Output spectrum with RF input f_RF=10.5 MHz and local oscillator f_LO=10 MHz at equal power. The presence of strong signal power at f_RF – f_LO=500 kHz and f_RF + f_LO=21.5 MHz clearly demonstrates mixing operations. All data are obtained using Agilent N9010A spectrum analyzer, and the measurements were done at room temperature in air.




1. K. S. Novoselov, et al., “Electric field effect in atomically thin carbon films” Science, vol. 306, pp. 666-669, Oct. 2004. [↩]
2. A. K. Geim, “Graphene: status and prospects,” Science, vol. 324, no. 5934, pp. 1530-1534, June 2009. [↩]
3. N. M. R. Peres, et al., “Electronic properties of disordered two-dimensional carbon,” Phys. Rev. B, vol. 73, pp. 125411, Mar. 2006. [↩]
4. K. Bolotin et al., “Ultrahigh electron mobility in suspended graphene,” Solid State Communications, vol. 146, pp. 351-355, June 2008. [↩]
5. H. Wang, D. Nezich, J. Kong, and T. Palacios “Graphene frequency multipliers,” IEEE Electron Device Lett., vol. ED-30, May 2009. [↩]
6. H. Wang, A. Hsu, J. Wu, J. Kong, and T. Palacios “Graphene-based ambipolar RF mixers,” IEEE Electron Device Lett., vol. ED-31, no. 9, Sept. 2010. [↩]

1.8-kV-breakdown AlGaN/GaN HEMT on Si Substrate

• Authors: M. Sun, Hyung-S. Lee, B. Lu, T. Palacios
• Sponsorship: DOE GIGA Program

The combination of high critical electric field, carrier mobility and thermal stability makes GaN an ideal semiconductor for power switches ^[1] . Additionally, the growth of GaN-based semiconductors on large area Si substrates significantly reduces the cost of these devices and enables their fabrication in state-of-the-art Si fabs. This paper demonstrates a GaN-on-Si HEMT with a 1.8-kV breakdown voltage and a record 2.4 mΩ,cm-2. specific on resistance.

The devices were fabricated on an AlGaN/GaN heterostructure grown on a 4-in Si substrate by MOCVD. The fabrication process began with plasma etching for device isolation; then a Ti/Al/Ni/Au metal stack was deposited on the source and drain contact region, followed by an 870°C rapid thermal annealing to form the ohmic contacts. Two-micron-long gate electrodes were deposited using Ni/Au/Ni. The devices have a gate-to-source distance of 1.5 μm and gate width of 100 μm. The gate-to-drain distance L-gd. varies from 5 μm to 35 μm.

Breakdown voltage measurements were carried out at a gate voltage Vg.=−8 V and with the samples immersed in Fluorinert to avoid surface flashover through air. The breakdown voltage Vbr. was defined as the voltage when the drain-to-source leakage current density I-D. exceeded 1 mA/mm. The breakdown voltage of the devices increases linearly with Lgd at a rate of 140 V/μm (Figure 1). However, the breakdown voltage saturates at Lgd.=12 μm due to vertical leakage through the Si substrate ^[2] . The maximum current density for a device with Lgd=12 μm is 375 mA/mm. Figure 2 shows the specific on resistance of the devices fabricated in this work as a function of breakdown voltage. This performance makes these devices very promising for power electronic applications including electric vehicles and photo-voltaic power inverters. Even higher breakdown voltage could be achieved by removing the substrate ^[2] ; this goal is the focus of our on-going work.



Figure 1: Breakdown voltage Vbr as a function of Lgd.



Figure 2: versus breakdown voltage for AlGaN/GaN power transistors on different substrates.




1. B. J. Baliga,  “Power semiconductor device figure of merit for high-frequency applications,” Electron Device Letters, IEEE, vol. 10, no. 10, pp. 455-457. [↩]
2. L. Bin and and T. Palacios. “High breakdown (>1500V) AlGaN/GaN HEMTs by substrate-transfer technology,” Electron Device Letters, IEEE, vol. 31, no. 9, pp. 951-953. [↩] [↩]

Low Temperature Gate Dielectric Deposition for Recessed AlGaN/GaN MIS-HEMTs

The use of gate dielectrics in AlGaN/GaN high electron mobility transistors (MIS-HEMTs) is attracting great interest for power applications since gate dielectrics improve the I_on/I_off ratio and reduce gate leakage in transistors. However, gate dielectrics prevent commonly used technologies like recessed gates. By using dielectrics deposited at low temperatures, we can design a self-aligned process in which the gate is lithographically patterned, the gate is recessed, and then the dielectric is deposited before the gate metal deposition. However, it has been reported that these dielectrics are of lower quality ^{[1] [2]} .  The purpose of this study is to investigate how dielectric material, deposition temperatures, and annealing conditions impact the quality of AlGaN/GaN MIS-HEMTs with low temperature gate dielectrics.

AlGaN/GaN/ MIS-HEMTs with HfO₂ and Al₂O₃ gate dielectrics were fabricated and studied with a reference Schottky gate transistor.  These dielectrics were deposited at temperatures ranging from 80 °C to 120 °C.  Following the gate metal deposition, different samples were annealed from 400C to 600C in either nitrogen or forming gas ambient.  The best HfO₂ transistors had a steeper subthreshold slope (71 mV/dec) than the best Al₂O₃ transistors (82 mV/dec) and the best Schottky gate transistors (142 mV/dec) as seen in Figure 1.   For all MIS-HEMTs, we found that annealing the transistors at 400 °C and increasing the deposition temperature improved the subthreshold slope the most.  In addition, we evaluated the I_on/I_off ratio of these transistors.  As seen in Figure 2, the devices with HfO₂ exhibited I_on/I_off ratios on the order of 10⁹, which was 4 orders higher than the best devices with Schottky gates.

To summarize, we show that by annealing low temperature gate oxides, low temperature MIS-HEMTs demonstrate performance better than Schottky gate transistors with respect to subthreshold slopes and I_on/I_off ratios.  These low temperature annealed oxides are very promising for combining fabrication technologies like submicron recessed gate transistors with gate dielectrics.



Figure 1: Correlation between subthreshold slope (S) and drain current in pinch-off for 120 °C HfO₂ devices. Note impact of annealing temperature on leakage current and subthreshold slope.



Figure 2: Impact of deposition temperature on the I_on/I_off ratio of transistors. Note that HfO₂ MIS-HEMTs have four orders-of- magnitude-higher I_on/I_off ratios than Schottky gate HEMTs with no dielectric.




1. M. D. Groner, F. H. Fabreguette, J. W. Elam, and S. M. George, “Low-temperature Al₂O₃ atomic layer deposition,” Chem Mater. vol. 16, no. 4, pp. 639-645, 2004. [↩]
2. D. J. Meyer, R. Bass, D. S. Katzer, D. A. Deen, S. C. Binari, K. M. Daniels, and C. R. Eddy Jr., “Self-aligned ALD AlO_x T-gate insulator for gate leakage current suppression in SiN_x-passivated AlGaN/GaN HEMTs,” Solid-State Electron., vol. 54, pp. 1098-1104, 2010. [↩]

GaN for Low Voltage Power Electronics

• Authors: D. Piedra, H.-S. Lee, T. Palacios
• Sponsorship: SRC/FCRP MSD, SRC/FCRP IFC, DOE GIGA Project

GaN-based transistors have outstanding properties for the development of ultra-high efficiency and compact power electronics.  The high electron mobility in the two-dimensional electron gas and the high critical electric field (greater than 10 times that of Si) make GaN high electron mobility transistors (HEMTs) ideal for power transistors ^[1] .  This work focuses on developing devices for operation below 200V.  We have developed a process to fabricate multi-finger AlGaN/GaN transistors with gate width of 39.6 mm (shown in Figure 1) that exhibit low on-resistance.

In addition to use in AlGaN/GaN HEMTs, the new technology has also been applied to InAlN/GaN devices.  By using InAlN as the barrier material, we take advantage of the high sheet charge density (N_s=2.5×10¹³ cm^-2) caused by higher polarization and reduced defect density of lattice-match InAlN barrier ^[2] .  The high sheet charge density results in low sheet resistance and high current density, which are ideal for low-loss, efficient power switches.  These devices have high breakdown voltage and excellent thermal stability due to the use of SiC substrates.  Additionally, our group has developed gold- free GaN transistor technology using ohmic recess and a Ti/Al/W metallization.  This technology is promising for the integration of GaN with silicon devices.



Figure 1: AlGaN/GaN multifinger HEMT with Wg=39.6 mm.



Figure 2: InAlN/GaN HEMT with varying gate widths.




1. U. Mishra, L. Shen, T. Kazior, and Y. Wu, “GaN-based RF power devices and amplifiers,” Proc. IEEE, vol. 96, no. 2, Feb. 2008. [↩]
2. F. Medjdoub, J.-F. Carlin, M. Gonschorek, E. Feltin, M. A. Py, D. Ducatteau, C. Gaquiére, N. Grandjean, and E. Kohn, “Can InAlN/GaN be an alternative to high power/ high temperature AlGaN/GaN devices?” Proc. IEDM Tech. Dig, 2006, pp. 927-930. [↩]

Graphene-based Chemical and Biological Sensors

• Authors: B. Mailly Giacchetti, K.-K. Kim, J. Kong, T. Palacios
• Sponsorship: Institute for Soldier Nanotechnologies

Thanks to its all-surface 2D structure combined with a very high carrier mobility, graphene is a very promising candidate for high sensitivity and low noise chemical sensing ^{[1] [2]} . Indeed, graphene devices can perform electrical detection for chemical sensing in a wide variety of applications, including pH monitoring in electrolytes ^{[3] [4]} ; glucose measurements in blood; and in-vitro recording of the electrical activity of living cells ^[5] .

Our group has developed the first solution-gated graphene field effect transistor (SGFET) arrays. These devices have important advantages with respect to traditional sensors, including intrinsic signal amplification, simple electronic read-out, and straightforward integration with microelectronics. Figure 1 shows a diagram of the graphene biosensor device and operating procedure. We use graphene grown by chemical vapor deposition as the active channel of these new devices. After fabricating graphene transistors with our standard technology, an SU8-based encapsulation technology has been developed to protect the contacts and wires from the electrolyte.

As seen in Figure 2.a), the characterization of our devices in a phosphate buffer solution displays high transconductances around 5 mS.mm^-1 (or 6 mS.V^-1 if normalized by the drain-source voltage). This high response highlights the very good sensitivity of our sensor compared to the conventional silicon devices, which typically have 20 times lower transconductances. The pH measurements have been performed using these devices, by recording how the Dirac point shifts with changes in pH, as shown in Figure 2.b). Sensitivity as high as 30 mV/pH have been demonstrated in this way. In addition, long term pH monitoring was shown for the first time in graphene devices, as shown in Figure 2.c). Our on-going work focuses on functionalizing graphene to demonstrate new biosensors focused on glucose detection. We are also optimizing the fabrication process to improve the sensitivity and decrease the noise of the devices.



Figure 1: Schematic illustration of the experimental setup for graphene solution-gated FET.



Figure 2: Graphene transistor, 9×60 mm² in size, a) Drain-source current change with electrolyte gating voltage V_g in 10 mM phosphate buffer, drain-source voltage V_DS=50mV. b) Dirac point shift with pH. c) Drain-source current versus time data for values of pH between 10 and 3.5 with V_g=0.4V and V_DS=10mV.




1. M. Dankerl, M. V. Hauf, A. Lippert, L. H. Hess, S. Birner, I. D. Sharp, A. Mahmood, P. Mallet, J. Veuillen, M. Stutzmann, and J. A. Garrido, “Graphene solution-gated field-effect transistor array for sensing applications,” Adv. Funct. Mater., vol. 20, pp. 3117-3124, Sep. 2010. [↩]
2. B. Mailly Giacchetti, A. Hsu, H. Wang, K. K. Kim, J. Kong, and T. Palacios, “CVD-grown graphene solution-gated field effect transistors for pH sensing,” MRS Proceedings, vol. 1283, 2011. [↩]
3. Y. Ohno, K. Maehashi, Y. Yamashiro, and K. Matsumoto, “Electrolyte-gated graphene field-effect transistors for detecting pH and protein absorption,” Nano Lett., vol. 9, pp. 3318-3322, Sep. 2009. [↩]
4. P. K. Ang, W. Chen, A. T. Wee, and K. P. Loh, “Solution-gated epitaxial graphene as pH sensor,” J. Am. Chem. Soc., vol. 130, pp. 14392-14393, Nov. 2008. [↩]
5. T. Cohen-Karni, Q. Qing, Q. Li, Y. Fang, and C. M. Lieber, “Graphene and nanowire transistors for cellular interfaces and electrical recording,” Nano Lett., vol. 10, pp. 1098-1102, Mar. 2010. [↩]

Gate Recessed Technology for Normally-off GaN Transistors

• Authors: B. Lu, T. Palacios
• Sponsorship: ARPA-E ADEPT

AlGaN/GaN high electron mobility transistors (HEMTs) have attracted a great interest for the next generation of power electronics due to their high electron mobility and high critical electric field. The standard AlGaN/GaN HEMTs are depletion-mode (D-mode) devices. However, enhancement-mode (E-mode) devices are highly desirable for power electronics as they can greatly simplify circuit designs and improve system reliability.

We have demonstrated a new AlGaN/GaN E-mode HEMT based on a dual-gate structure ^[1] . In this structure, the impact of the gate recess to the device on-resistance has been minimized by shrinking the recessed gate length. In the first version of the device, however, the channel electron mobility of the recess gate region was very poor, ~ 20 cm²/V^.s. In order to improve the normally-off device channel mobility and uniformity of the threshold voltage, an improved device structure has been designed ^[2] . The new device structure is shown in Figure 1; it uses a GaN/AlN spacer between the AlGaN barrier and GaN channel in the conventional AlGaN/GaN HEMTs. The benefits of the GaN/AlN spacer structure are good channel transport property and high uniformity of threshold voltage. To fabricate E-mode devices, the AlGaN layer is removed from the gate region to deplete the channel. Then a selective etching between GaN and AlN can be used to stop the gate recess at the AlN layer, resulting in a uniform threshold voltage across the wafer. The AlN layer also prevents the gate dielectric from direct contacting the channel, reducing electron trapping and improving channel mobility.

In order to fabricate the dual-gate transistor, a double gate recess must be used to prevent overheating of the photoresist during gate recess and improve the threshold voltage matching ^[1] in the dual-gate structure. The double-gate-recess process illustrated in Figure 2 allows a robust and flexible gate-recess technology for excellent normally-off operation.



Figure 1: Schematic cross-section of E-mode GaN transistor using GaN/AlN spacer with dual-gate structure.



Figure 2: Double gate recess process.




1. B. Lu and T. Palacios, “High performance integrated dual-gate AlGaN/GaN enhancement-mode transistor,” IEEE Elec. Dev. Lett., vol. 31, no. 9, pp. 990-992, Sep. 2010. [↩] [↩]
2. B. Lu and T. Palacios, “Enhancement-mode Nitride Transistor,” U.S. Pat. 12574146, filed Oct. 6, 2009. [↩]

Heterogeneous Integration of GaN and Si Devices

• Authors: H.-S. Lee, K. Ryu, T. Palacios
• Sponsorship: DARPA

Gallium nitride (GaN) is a wide bandgap semiconductor with unsurpassed properties for high voltage switches and RF amplifiers. However, in spite of their excellent performance, GaN devices cannot compete with the integration density and complexity of modern Si CMOS electronics. The integration of GaN and Si (100) devices on the same chip would, therefore, enable a vast array of new applications, from novel power distribution schemes in Si microsystems, to power digital-to-analog converters and new opportunities for optoelectronic devices integrated on a Si platform.

Our GaN-Si integration approach is based on a full 4” wafer bonding ^[1] , where a thin layer of high-quality Si (100) is transferred to the top of a GaN-on-Si (111) wafer. These new hybrid wafers look akin to SOI wafers, except that instead of silicon underneath the oxide, there is a GaN device layer. Using this approach, PMOS devices and GaN HEMTs have been fabricated on the same wafer. Figure 1 (left) shows a cross-sectional view of the bonded 4” GaN and Si wafers. Once the hybrid wafer has been fabricated, a standard Si process technology was used for the fabrication of the Si devices.  After the fabrication of the Si devices, windows are opened to expose the III-N epilayer in the regions where GaN HEMTs are required.  Figure 1 (right) shows the optical microscope image of a fabricated a Si PMOS and a GaN HEMT devices in close proximity. Figure 2 (top) shows the typical output characteristics of a Si pMOSFET with gate length (Lg) of 3 µm and a GaN HEMT with Lg=3.2 µm. A GaN HMET shows a less than 5% difference with a reference HEMT, indicating that this integration process using hybrid wafers has not been influenced on the device characteristics due to the high thermal stability of the fabricated Si/GaN/Si wafers.



Figure 1: Scanning electron microscope (SEM) image of the cross-sectional view of a Si-GaN-Si bonded wafer (left). Optical image of the fabricated Si PMOS and GaN HEMT on a 4-inch Si(100)-GaN-Si(111) hybrid wafer (right).



Figure 2: DC output characteristics of a Si pMOSFET with Lg=3 µm (top) and GaN HEMTs with Lg=3.2 µm (bottom).




1. K. Ryu, J. Chung, B. Lu, and T. Palacios, “Wafer bonding technology in nitride semiconductors for applications in energy and communications,” ECS Transactions, vol. 33, no. 4, pp. 125-135, 2010. [↩]

Top-down Fabrication of N-face GaN/AlGaN Nanowire HEMTs

• Authors: M. Azize,, K. K. Ryu, J. Roberts, E. L. Piner, T. Palacios|
• Sponsorship: Office of Naval Research, National Science Foundation

The high-frequency performance of Ga-face Al_xGa_1–xN/GaN high electron mobility transistors (HEMTs) has rapidly increased in recent years, enabling use of these devices in power amplifiers for mm-wave applications ^[1] . However, this frequency performance is still far from the theoretical limit due to poor gate modulation efficiency, short channel effects and high access resistances. With their reversed polarization, N-face GaN/AlGaN transistors have a tremendous potential to improve device performance ^[2] . At the same time, nanowire (NW)-based HEMTs could also help to overcome many of these limitations and increase the maximum frequency of nitride devices by improving the electron confinement and reducing short channel effects ^[3] . Therefore, the combination of both N-face material and NW structures in the same device would offer new flexibility for high-frequency power amplifiers. We are developing NW-based nitride HEMTs to explore the maximum frequency performance of nitride devices ^[3] .

Our starting material is a Ga-face AlGaN (~17 nm)/GaN (~25 nm) /AlGaN (~5 nm)/GaN (~1.8 mm) HEMTs grown on Si(111) substrate by metal organic vapor phase epitaxy. After growth, the Ga-face of the wafer is bonded to a carrier substrate; dry etching removes the original substrate and GaN buffer to expose the N-face of the GaN/AlGaN structure (see Figure 1). With a 5-nm-thick etch stop layer, all GaN buffer can be removed, leaving only 47 nm of AlGaN/GaN/AlGaN structure. Free-standing NW devices are fabricated in a two-step, top-down technology ^[4] . Standard planar transistors are first fabricated; via electron-beam lithography, arrays of lateral NWs are patterned between two Ohmic contacts. Electron cyclotron resonance reactive ion etching removes the material between adjacent NWs by using BCl₃ and Cl₂ chemistry. The etch depth is ~ 50 nm, deep enough to prevent electrical conduction between NWs. A maximum drain current of ~600 mA/mm is measured in the fabricated NW-based HEMTs (see Figure 2). This current density is ~20% higher than current in a planar N-face HEMT, used as a reference. Characterization of the high frequency performance of these nanowires is currently underway. We expect that the large carrier confinement of these devices will allow higher operating frequencies as well as linearity. ^[5]



Figure 1: Main processing steps of the layer transfer technology used to obtain N-face GaN epilayers.



Figure 2: Ids-Vds characteristics of N-face planar and NW HEMTs. The current in NW devices is also normalized to the effective diameter (i.e., conducting channel) for a direct comparison between planar and NW-based HEMTs.




1. J. W. Chung, W. E. Hoke, E. M. Chumbes, and T. Palacios, IEEE Electron Device Lett. vol. 31, p. 3, 2010. [↩]
2. S. Rajan, A. Chini, M. H. Wong, J. S. Speck, and U. K. Mishra, J. Appl. Phys., vol. 102, p. 44501, 2007. [↩]
3. B. Yu, Y. Yuan, J. Song and Y. Taur, IEEE Transactions on Electron Dev. vol. 56, p 2357, 2009. [↩] [↩]
4. M. Azize and T. Palacios, App. Phys. Lett., vol. 98, p. 042103, 2011.2011. [↩]
5. J. W. Chung, E. L. Piner, and T. Palacios, IEEE Electron Device Lett. vol. 30, p. 113, 2009. [↩]

Synthesis of One- to Two-layer Hexagonal Boron Nitride Using Chemical Vapor Deposition

• Authors: K. K. Kim, Y. Shi, A. Hsu, M. Hofmann, D. Nezich, X. Jia, S. M. Kim, S. M. Jung, M. Dresselhaus, T. Palacios, J. Kong
• Sponsorship: National Science Foundation, GATE-MURI



Figure 1: (a-d) Transmission electron microscopy images of one to two layers of hexagonal boron nitride (hBN) film, (e) Selective electron diffraction pattern of hBN film, (f) Electron energy loss spectra of hBN film.

Hexagonal boron nitride (hBN) is very attractive for a variety of applications, particularly as deep ultraviolet emitter, transparent membrane, dielectric layer/substrate, or protective coating. In this work, we carried out detailed investigation of hBN synthesis on Cu substrate using chemical vapor deposition (CVD) with two heating zones under low pressure (LP).  Previously, few-layer hBN was synthesized via CVD under atmospheric pressure (AP) on metallic substrates ^{[1] [2]} .  In contrast, one- or two-layer hBN is synthesized under LPCVD. Ammonia borane, which is easier accessible and more stable in the atmosphere than borazine, is used as a BN precursor. These mono- or bi-layer hBN films are characterized by atomic force microscopy, transmission electron microscopy and electron energy loss spectroscopy analyses.  Our results suggest that the growth here occurs via surface-mediation, which is similar to graphene growth on Cu under low pressure. These atomically thin layers are particularly attractive for atomic membranes or dielectric layer/substrates for graphene devices.

1. Y. M. Shi, C. Hamsen, X. T. Jia, K. K. Kim, A. Reina, M. Hofmann, A. L. Hsu, K. Zhang, H. N. Li, Z. Y. Juang, M. S. Dresselhaus, L. J. Li, and J. Kong, “Synthesis of few-layer hexagonal boron nitride thin film by chemical vapor deposition,” Nano Letters, vol. 10, pp. 4134-4139, Oct. 2010. [↩]
2. L. Song, L. Ci, H. Lu, P. B. Sorokin, C. Jin, J. Ni, A. G. Kvashnin, D. G. Kvashnin, J. Lou, B. I. Yakobson, and P. M. Ajayan, “Large scale growth and characterization of atomic hexagonal boron nitride layers,” Nano Letters, vol. 10, pp. 3209-15, Aug. 2010. [↩]