All entries for Jesus del Alamo

Jesús A. del Alamo

Title: Donner Professor and MacVicar Faculty Fellow
Department: Department of Electrical Engineering and Computer Science

Collaborators

J. Jimenez, Triquint Semicon
D.H. Kim, Teledyne
Y. Knafo, Gal El
A. Valdes, IBM

Postdoctoral Fellow

J. Joh
T. W. Kim

Graduate Students

U. Gogineni, Res. Asst., EECS
D.H. Jin, Res. Asst., EECS
L. Xia, Res. Asst., EECS
S. Demirtas, Res. Asst., EECS
X. Zhao, Res. Asst., DMSE
A. Guo, Res. Asst. EECS
J. Lin, Res. Asst. EECS

Support Staff

E. Kubicki, Admin. Asst. II

Publications

Kim, T.-W., D.-H. Kim, and J. A. del Alamo, “60 nm Self-Aligned-Gate InGaAs HEMTs with Record High-Frequency Characteristics,” IEEE International Electron Devices Meeting, San Francisco, CA, December 6-8, 2010, pp. 696-699.

Kim, D.-H., J. A. del Alamo, P. Chen, W. Ha, M. Urteaga and B. Brar, “50 nm E-Mode In0.7Ga0.3As PHEMTs on 100 mm InP Substrate with fmax>1 THz,” IEEE International Electron Devices Meeting, San Francisco, CA, December 6-8, 2010, pp. 692-695.

Joh, J. and J. A. del Alamo, “RF Power Degradation of GaN High Electron Mobility Transistors,” IEEE International Electron Devices Meeting, San Francisco, CA, December 6-8, 2010, pp. 468-471.

Joh, J., P. Makaram, C. V. Thompson, and J. A. del Alamo, “Planar View of Structural Degradation in GaN High Electron Mobility Transistors: Time and Temperature Dependence,” Invited talk at International Workshop on Nitride Semiconductors (IWN 2010), Tampa, FL, 2010.

Kim, D.-H. and J. A. del Alamo, ”30 nm InAs PHEMTs with fT=644 GHz and fmax=681 GHz,” IEEE Electron Device Letters, vol. 31, no. 8, pp. 806-808, August 2010.

Kim, D.-H. and J. A. del Alamo, ”Scalability of sub-100 nm InAs HEMTs on InP Substrate for Future Logic Applications,” IEEE Transactions on Electron Devices, vol. 57, no. 7, pp. 1504-1511, July 2010.

Makaram, P., J. Joh, J. A. del Alamo, T. Palacios, C. V. Thompson, ”Evolution of Structural Defects Associated with Electrical Degradation in AlGaN/GaN HEMTs,” Applied Physics Letters, vol. 96, p. 233509, 2010.

Wu, J. H., and J. A. del Alamo, ”Fabrication and Characterization of through-Substrate Interconnects,” IEEE Transactions on Electron Devices, vol. 57, no. 6, pp. 1261-1268, June 2010.

Kim, T.-W., D.-H. Kim and J. A. del Alamo, “Logic Characteristics of 40 nm thin-channel InAs HEMTs,” 22nd International Conference on Indium Phosphide and Related Materials, Kagawa, Japan, May 31-June 4, 2010, pp. 496-499.

Xia, L. and J. A. del Alamo, “Mobility enhancement in Indium-rich N-channel InxGa1-xAs HEMT by Application of <110> Uniaxial Strain,” 22nd International Conference on Indium Phosphide and Related Materials, Kagawa, Japan, May 31-June 4, 2010, pp. 504-507.

Joh, J. and J. A. del Alamo, “Reliability and Failure Mechanisms of GaN-based HEMTs,” Invited talk at 10th Expert Evaluation and Control of Compound Semiconductor Materials and Technologies (EXMATEC 2010), Darmstadt/Seeheim, Germany, May 19-21, 2010, pp. 57-58.

Joh, J., J. A. del Alamo, K. Langworthy, S. Xie, and T. Zheleva, “Correlation between electrical and material degradation in GaN HEMTs stressed beyond the critical voltage,” Microelectronics Reliability, vol. 51, pp. 201-206 (2011).

Demirtas, S. and J. A. del Alamo, “Effect of Trapping on the Critical Voltage for Degradation in GaN High Electron Mobility Transistors,” 2010 International Reliability Physics Symposium, Anaheim, CA, May 2-6, 2010, pp. 134-138.

Gogineni, U., H. Li, J. A. del Alamo, S. Sweeney, J. Wang, and B. Jagannathan, ”Effect of Substrate Contact Shape and Placement on RF Characteristics of 45 nm Low Power CMOS Devices,” IEEE Journal of Solid State Circuits, vol. 45, no. 5, pp. 998-1006, May 2010.

del Alamo, J. A. and D.-H. Kim, “The prospects for 10 nm III-V CMOS,” Invited talk at 2010 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Taiwan, April 26-28, 2010, pp. 166-167.

Gogineni, U., J. A. del Alamo, and C. Putnam, “RF Power Potential of 45 nm CMOS Technology,” 10th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF 2010), New Orleans, LA, January 11-13, 2010, pp. 204-207.

Waldron, N., D.-H. Kim and J. A. del Alamo, ”A Self-Aligned InGaAs HEMT Architecture for Logic Applications,” IEEE Transactions on Electron Devices, vol. 56, no. 1, pp. 297-304, January 2010.

Transistors with Steep Subthreshold Characteristics Based on Impact Ionization on Narrow Bandgap Semiconductors

Authors: X. Zhao, J. A. del Alamo
Sponsorship: NSF Center for Energy Efficient Electronics Science (E3S)

Achieving a sharp subthreshold swing is crucial to enable the supply voltage scaling that is necessary for reducing power consumption in logic field-effect transistors. In this research, we are investigating a new approach to accomplish this goal based on impact ionization (II) on III-V narrow bandgap semiconductors.

In n-type partially-depleted floating body silicon-on-insulator transistors, a subthreshould swing less than the theoretical minimum value of 60 mV/decade at room temperature has been observed at relatively high drain bias^[1]. This steep swing is attributed to holes generated due to II at the drain side that are swept back towards the source and pile up at the source end of the channel (under the gate). As a consequence of this piling-up, the body-source diode gets positively biased and more electrons are injected into the channel. The additional electrons, in turn, produce more holes. This positive feedback is the reason for a steep subthreshold swing. However, due to large bandgap and low II rate in silicon, a high drain bias is needed. This phenomenon is also associated with slow dynamics. In narrow bandgap materials, such as InAs where the ionization threshold is low and the ionization rate is high^[2], these difficulties could possibly be overcome.

Our current efforts in this area have been focused on the characterization of II in existing III-V FETs, in order to gain a comprehensive understanding of the physics. In our AlGaAs/In_0.15Ga_0.85As/AlGaAs high electron mobility transistors we have observed a classical signature of II. Our data shows a characteristic bell-shaped I_G-V_GS curve^[3] and a negative temperature dependence. In Figure 1, I_G/I_D has an exponential dependence on (V_DS-V_DSAT)^-1, which follows a classical model^[4]. In a parallel effort, we are developing a simulation environment suitable for III-V transistors that can correctly capture impact ionization and its consequences. Preliminary simulated subthreshold characteristics are shown in Figure 2 and compared with measured characteristics.

Transistors with higher InAs composition will be investigated in the future in terms of dynamics, kink effect, gate current, etc. A more suitable simulation environment will also be pursued. Based on this understanding, we will propose and fabricate transistor structures that best exploit impact ionization to realize steep subthreshold characteristics.

J. R. Davis, A. E. Glaccum, K. Reeson, and P. L. F. Hemment, “Improved subthreshold characteristics of n-channel SOI transistors,” IEEE Electron Device Letters, vol. Edl-7, no. 10, Oct. 1986. [↩]
J. Bude and K. Hess, “Thresholds of impact ionization in semiconductors,” Journal of Applied Physics, vol. 72, no. 8, July, 1992. [↩]
A. A. Moolji, S. R. Bahl, and J. A. del Alamo, “Impact ionization in InAlAs/InGaAs HFET’s,” IEEE Electron Device Letters, vol. 15, no. 8, Aug. 1994. [↩]
K. Hui, and C. Hu, “Impact ionization in GaAs MESFET’s,” IEEE Electron Device Letters, vol. 11, no. 3, Mar. 1990. [↩]

Hole Mobility Enhancement in III-V FETs through Uniaxial Strain

Authors: L. Xia, J. A. del Alamo
Sponsorship: Intel, SRC/FCRP MSD

In Si p-type metal-oxide-semiconductor field-effect transistors (MOSFETs), the incorporation of mechanical strain in the channel has greatly enhanced hole velocity and transistor performance. As conventional Si MOSFET scaling gets increasingly difficult, III-V FETs are receiving a great deal of attention for a future sub-10-nm complementary MOS (CMOS) logic technology. In fact, in some measure, n-channel III-V FETs have been found to outperform Si MOSFETs with gate lengths down to 30 nm. To complement these n-channel III-V FETs, we are investigating high-performance p-channel III-V FETs. Given that the hole mobility of most III-Vs is at best comparable to that of Si, strain is being investigated as a path to enhance the hole mobility and consequently III-V pFET performance. In our present work, we experimentally study the potential to improve p-channel III-V FETs by introducing uniaxial strain into these devices.

To introduce controlled uniaxial strain into FETs, we designed and fabricated a mechanical apparatus (Figure 1) to bend III-V chips. This apparatus allows the application of uniaxial strain up to ±0.3% to III-V chips. Electrical measurements on FETs can be performed while the chips are bent. In addition, Hall measurements can also be carried out by applying a magnetic field with a pair of permanent magnets. These allow the direct evaluation of strain effects on the hole mobility and hole concentration.

The structures we studied include p-channel FETs and ungated Hall bars based on InGaSb^[1], GaAs^[2] and InGaAs^[3]. The devices were either supplied by our collaborators or fabricated at MIT. Figure 2 shows an example of an InGaSb quantum-well FET (QW-FET) structure we have studied and its response to applied uniaxial stress^[1]. As shown in the figure, stress significantly changes the operation of the device. In fact, we found that changes occur in the device drain current and threshold voltage. These changes are the manifestations of changes in hole mobility and hole concentration. The change in hole mobility shares similar physics with what has been found earlier in Si and Ge pFETs. The hole concentration change is due to the stress-induced piezoelectric field. The piezoelectric effect does not exist in Si or Ge FETs but is found to be important to consider in III-V FETs. The magnitude of stress-induced hole mobility enhancement in our III-V FETs has been found comparable to or even larger than those in Si and Ge pFETs. The maximum hole mobility change was found to be 12% per 100 MPa stress in a In_0.24Ga_0.76As quantum well, which is 70% higher than in Si p-MOSFETs. Our work suggests that uniaxial stress is a viable path to enhance hole mobility in high-performance p-channel III-V FETs.

: Figure 1: Chip-bending apparatus to introduce uniaxial strain into III-V FETs. This setup allows repeatable electrical measurements with III-V chips stressed at various levels. In addition, Hall measurements can be conducted with a magnetic field applied.

: Figure 2: (Left) The cross section of a p-channel In_0.41Ga_0.59Sb quantum-well FET (QW-FET). (Right) Measured transfer characteristics change of the QW-FET with <110> uniaxial stress applied by our mechanical apparatus.

L. Xia, J. B. Boos, B. R. Bennett, M. G. Ancona, and J. A. del Alamo, “Hole mobility enhancement in In_0.41Ga_0.59Sb quantum-well field-effect transistors,” Applied Physics Letters, vol. 98, p. 053505, 2009. [↩] [↩]
L. Xia, V. Tokranov, S. R. Oktyabrsky, and J. A. del Alamo, “Experimental study of <110> uniaxial stress effects on P-channel GaAs quantum-well FETs,” To be published on IEEE Transaction of Electron Devices. [↩]
L. Xia, V. Tokranov, S. Oktyabrsky, and J. A. del Alamo, “Mobility enhancement of two-dimensional hole gas in an In_0.24Ga_0.76As quantum well by <110> uniaxial strain,” Proc. International Symposium of Compound Semiconductor, p. 396, 2011. [↩]

A Self-aligned Gate Technology for InGaAs Quantum-well Field-effect Transistors

Authors: T.-W. Kim, J. A. del Alamo (in collaboration with D.-H. Kim, Teledyne Scientific Company)
Sponsorship: SRC/FCRP MSD, Intel Corporation

As conventional Si CMOS scaling approaches the end of the roadmap, III-V based field-effect transistors appear as an increasingly viable alternative to continue transistor size scaling. A great deal of the excitement about the prospects of III-Vs comes from the excellent logic characteristics that have recently been demonstrated in InGaAs high electron mobility transistors (HEMTs) with gate length as small as 30 nm. While being quite far in structure from an ideal logic III-V MOSFET, the HEMT has been demonstrated to be an excellent model system to study fundamental device physics and technology issues. It also has provided well-calibrated and relatively parasitic-free device results to support the development of simulators that would allow us to chart the future of a III-V logic technology. In this regard, there is great value in continuing to push the scaling of HEMTs to explore significant device physics issues in the relevant dimensional range. Until now, the demonstrated HEMTs have had a quite large gate-source distance of around 1 mm and a source resistance of around 200 ohm-mm. These are large values compared with state-of-the-art Si CMOS technology. To address these deficiencies, a self-aligned gate scheme is essential.

Our group has been engaged in self-aligned gate technologies for III-V FETs for several years^[1]^[2]. In our first approach, W was used as non-alloyed ohmic contacts with the gate nested inside an opening in a self-aligned way. Through this technology, 90-nm gate length InGaAs HEMTs were demonstrated with L_GS = 60 nm. This technology featured a simple lift-off gate with high parasitic capacitance. As a result, the frequency response of the fabricated transistors was unremarkable. In this work, we demonstrate a new self-aligned gate technology with non-alloyed Mo-based ohmic contacts and a very low parasitic capacitance gate design. The proposed device architecture allows for the incorporation of a high-K gate dielectric in the gate stack to achieve MOS-type devices. The new process delivers very low values of contact resistance and source resistance plus record high-frequency characteristics. We have obtained a contact resistance (R_c) of about 7 ohm-mm, which is a near-record result. The contact is thermally stable up to 600°C. Figure 1 shows STEM images of a fabricated L_g = 60-nm device. Figure 2 shows short-circuit current-gain cut-off frequency f_T as a function of L_g for sub-100-nm InGaAs and InAs HEMTs. The obtained f_T value in our device is the highest ever reported in a HEMT with a gate length above L_g = 50 nm and bodes well for the future scalability of this device design. This result strongly suggests a path towards the demonstration of III-V MOSFETS for future CMOS.

: Figure 1: Cross-section STEM images of Mo-based SAG HEMT with L_g = 60 nm with 100-nm gate-source contact separation.

: Figure 2: The f_T as a function of L_g for reported InGaAs and InAs HEMTs in the literature, including Mo-based SAG HEMTs in this work.

N. Waldron et al. “A self-aligned InGaAs HEMT architecture for logic applications,” IEEE Tran. Electron Devices, vol. 57, no. 1, pp. 297-304, 2010. [↩]
T.-W. Kim et al. “60 nm Self-aligned-gate InGaAs HEMTs with record high-frequency characteristics,” IEDM, pp. 696-699, 2010. [↩]

High Voltage Degradation of GaN HEMTs for Power-switching Applications

Authors: D. Jin, J. A. del Alamo
Sponsorship: ARPA-E

The GaN high-electron-mobility transistor (HEMT) is a very promising device for power-switching applications due to the outstanding material properties of GaN such as high band-gap (3.4 eV) and high breakdown electric field (> 3×10⁶ V/cm), which enable these devices to achieve a very high breakdown voltage. However, the wide deployment of GaN HEMT technology is limited mostly by its electrical reliability. The lack of a native substrate for GaN epitaxial growth (SiC or Si are mostly used) means that a large density of mismatch defects might be present in the active device area, potentially introducing carrier trapping and compromising its electrical reliability. Trapping, in particular, is a significant problem in high-voltage switching devices. When the device is biased at a high blocking voltage in the OFF-state, electron trapping takes places over a large volume of the semiconductor. This trapping can cause a large increase of the on-resistance (R_ON) or a subsequent drain current drop. This problem is known as dynamic R_ON, or current collapse phenomenon^[1], which is one of the most prevalent degradation issues in GaN HEMTs. A high electric field in the OFF-state also induces a large amount of mechanical stress and above a certain critical value, crystallographic defects are formed which result in further enhanced electron trapping and subsequent current collapse^[2]. These unique reliability issues are the key hurdle for the commercialization of this new disruptive technology.

Our research focuses mainly on the electrical reliability of GaN HEMTs specially designed for high voltage operation up to 200 V. Our systematic characterization experiments extract important figures of merits such as linear drain current (I_Dlin), gate leakage current in the OFF state (I_Goff), drain resistance (R_D), source resistance (R_S) and threshold voltage (V_T) as a device is being degraded. Figures 1 and 2 show the time evolution of I_Dlin, R_D and R_S in a step-stress-recovery experiment in the OFF-state at room temperature. A 5-min stress period is followed by 5-min recovery period under microscope light illumination. For each stress period, V_GS= -5 V and V_DS is incremented from 30 V to 150 V in 30-V steps. During the stress periods, I_Dlin/R_D decreases/increases as V_DS stress voltage goes up to 90 V. Above 90 V, however, the degradation in I_Dlin and R_D is mitigated. During the recovery periods under visible light, I_Dlin and R_D fully recover back to the original value before the stress. These results support a hypothesis in which trapping and detrapping are taking place during the stress and recovery periods, but no permanent damage is being introduced. From separate experiments we have learned that the traps involved are all native traps; that is, no new traps are being created as a result of high-voltage stress. Since these trapping and detrapping dynamics are most relevant in determining dynamic R_ON during the high frequency switching operation, a precise understanding of this behavior under high voltage stress in a much shorter time scale is of great importance.

: Figure 1: Time evolution of I_Dlin and stress voltage (V_DSstress) in a step-stress-recovery experiment in the OFF-state in GaN HEMTs. V_DS is step stressed from 30 V to 150 V in 30-V steps and 5-min stress periods. A 5-min recovery period under visible light illumination follows each stress period. Trapping is evident but no permanent I_Dlin degradation is observed.

: Figure 2: Time evolution of R_D and R_S in the step-stress-recovery experiment of Figure 1. The full recovery of R_D and R_S indicates trapping effects that involve only native traps.

J. A. del Alamo and J. Joh, “GaN HEMT reliability,” Microelectronics Reliability, vol. 49, pp. 1200-1206, 2009. [↩]
J. Joh and J. A. del Alamo, “Impact of electrical degradation on trapping characteristics of GaN high electron mobility transistors,” International Electron Devices Meeting Technical Digest, pp. 461-464, Dec. 2008. [↩]

Nano-scale Metal Contacts for Future III-V CMOS

Authors: A. Guo, T.–W. Kim, J. A. del Alamo
Sponsorship: Sponsorship: SRC/FCRP MSD

Figure 1: Cross section image of a nano-TLM structure. Metal line with contact length 230nm and spacing 780nm was observed after ebeam lithography, metal lift-off and mesa etching steps. Image was taken using Zeiss Supra-40 scanning electron microscope.

The scaling of MOSFETs in recent years has pushed the gate length down to less than 20 nanometers. Further gate length scaling is extremely challenging due to worsened short channel effects at the nanometer scale. Recently, much effort has been put into new device materials and structures to extend scaling trend for several more generations. Among others, III-V CMOS has shown promising results. One of the key elements for a high performance, small footprint III-V CMOS technology is a nanometer scale metal contact with low contact resistance. This study focuses on developing such a contact. To help us better understand ohmic contact properties in the quantum regime, this study explores the contact properties of Mo-based metallization on a III-V semiconductor substrate in the nanometer scale. The goals of the project are to develop a fabrication process that will produce good ohmic contact down to 50-nm contact length and to study the metal contact characteristics in the quantum regime.

Our approach consists on fabricating a nano-TLM (transmission line model) structure. The key step in this is defining thin metal lines using e-beam lithography technique. A Mo/Ti/Au contact is then e-beam evaporated. A lift-off process will follow to form nanometer scale metal lines and contacts. For device characterization, four 150-µm by 150-µm contact pads are designed to overlay on top of the metal lines to evaluate the contact resistance using Kelvin-type TLM measurements. Figure 1 shows the preliminary result of metal lines with 230nm contact length and a spacing of 780nm. The undercut defined the mesa width and the contact width of these metal lines. In the near future we expect to adapt nano-scale ohmic contact into III-V MOSFETs process, which will reduce the chip’s footprint and provide insight into the contact characteristics in the quantum regime.

A Self-aligned InGaAs Quantum-well Field-effect Transistor for Logic Applications

Authors: J. Lin, J. A. del Alamo, D. A. Antoniadis
Sponsorship: Sponsorship: SRC/FCRP MSD

InGaAs is a promising candidate for channel material for future high-performance CMOS logic applications because of its superior electron transport properties^[1]. InGaAs quantum-well metal-oxide-semiconductor field-effect transistor (QW-MOSFET) research has recently attracted great interest from the IC device community. N-channel InGaAs-based High-electron-mobility transistors (HEMTs) fabricated previously at MIT have served as an excellent testbed with which to explore issues of importance in a future III-V CMOS technology. They demonstrated outstanding logic device characteristics due to the high injection velocity at low supply voltage and high electrostatic integrity afforded by the quantum-well channel^[1]^[2]^[3]. These advantages, if ported over to InGaAs MOSFETs, can eventually lead to integrated circuits exhibiting high speed with reduced power dissipation.

There are many challenges in the development of a InGaAs QW-MOSFET technology for future CMOS applications. For example, low series resistance and a compact footprint are required. In this work we prototype a novel self-aligned InGaAs QW-MOSFET that can address these problems. The cross-sectional schematic of the QW-MOSFET is shown in Figure 1. This device uses a thin Al₂O₃ gate dielectric. Molybdenum-based ohmic contacts are self-aligned to the gate. This self-alignment scheme reduces the spacing between the contacts and the gate and leads to a lower series resistance. A first working prototype QW-MOSFET with L_g =2 mm has been fabricated, and the output characteristics are shown in Figure 2. Process optimization, aimed at a further reduction in the source resistance, is being carried out. The scaling behavior and performance analysis with respect to silicon technology for this new device structure will be investigated.

: Figure 1: Cross-sectional schematic of self-aligned InGaAs QW-MOSFET.

: Figure 2: Output characteristics of a prototype QW-MOSFET with L_g =2 μm.

D.-H. Kim, J. A. del Alamo, D. A. Antoniadis, and B. Brar, “Extraction of virtual-source injection velocity in sub-100 nm III-V HFETs,” in IEDM Tech. Dig., pp. 861-864, Dec. 2009. [↩] [↩]
D.-H. Kim and J. A. del Alamo, “30 nm E-mode InAs PHEMTs for THz and future logic applications,” in IEDM Tech. Dig., pp. 719-722, Dec. 2008 [↩]
T.-W., Kim, D.-H. Kim, and J. A. del Alamo, “Logic characteristics of 40 nm thin-channel InAs HEMTs,” 22nd International Conference on Indium Phosphide and Related Materials, pp. 496-499, May 2010. [↩]

MTL Annual Research Report 2011