MTL Annual Research Report 2011

The GaN high-electron-mobility transistor (HEMT) is a very promising device for power-switching applications due to the outstanding material properties of GaN such as high band-gap (3.4 eV) and high breakdown electric field (> 3×10⁶ V/cm), which enable these devices to achieve a very high breakdown voltage. However, the wide deployment of GaN HEMT technology is limited mostly by its electrical reliability. The lack of a native substrate for GaN epitaxial growth (SiC or Si are mostly used) means that a large density of mismatch defects might be present in the active device area, potentially introducing carrier trapping and compromising its electrical reliability. Trapping, in particular, is a significant problem in high-voltage switching devices. When the device is biased at a high blocking voltage in the OFF-state, electron trapping takes places over a large volume of the semiconductor. This trapping can cause a large increase of the on-resistance (R_ON) or a subsequent drain current drop. This problem is known as dynamic R_ON, or current collapse phenomenon ^[1] , which is one of the most prevalent degradation issues in GaN HEMTs. A high electric field in the OFF-state also induces a large amount of mechanical stress and above a certain critical value, crystallographic defects are formed which result in further enhanced electron trapping and subsequent current collapse ^[2] . These unique reliability issues are the key hurdle for the commercialization of this new disruptive technology.

Our research focuses mainly on the electrical reliability of GaN HEMTs specially designed for high voltage operation up to 200 V. Our systematic characterization experiments extract important figures of merits such as linear drain current (I_Dlin), gate leakage current in the OFF state (I_Goff), drain resistance (R_D), source resistance (R_S) and threshold voltage (V_T) as a device is being degraded. Figures 1 and 2 show the time evolution of I_Dlin, R_D and R_S in a step-stress-recovery experiment in the OFF-state at room temperature. A 5-min stress period is followed by 5-min recovery period under microscope light illumination. For each stress period, V_GS= -5 V and V_DS is incremented from 30 V to 150 V in 30-V steps. During the stress periods, I_Dlin/R_D decreases/increases as V_DS stress voltage goes up to 90 V. Above 90 V, however, the degradation in I_Dlin and R_D is mitigated. During the recovery periods under visible light, I_Dlin and R_D fully recover back to the original value before the stress. These results support a hypothesis in which trapping and detrapping are taking place during the stress and recovery periods, but no permanent damage is being introduced. From separate experiments we have learned that the traps involved are all native traps; that is, no new traps are being created as a result of high-voltage stress. Since these trapping and detrapping dynamics are most relevant in determining dynamic R_ON during the high frequency switching operation, a precise understanding of this behavior under high voltage stress  in a much shorter time scale is of great importance.