All entries for Dimitri Antoniadis

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Virtual-source-based Self-consistent Charge and Transport Models for Ballistic MOSFETs

• Authors: L. Wei, O. Mysore, D. A. Antoniadis
• Sponsorship: SRC/FCRP MSD, DARPA

Compact models describing the voltage-dependent terminal current and charges (or equivalently, capacitances) are essential for small-signal and transient circuit simulation.  In this work, we extend the virtual-source (VS)-based transport model ^[1] with a self-consistent channel charge model for quasi-ballistic or fully ballistic devices, when the gradual channel approximation (GCA) and the drift transport theory are no longer valid. From a parabolic channel potential profile approximation and current continuity boundary condition, we derive a voltage-dependent charge model that is self-consistent with the transport model in the ballistic regime. The extended VS model has been implemented in Verilog-A language. ^[2]

Devices operating in the ballistic regime in saturation have less channel charge than predicted by the drift-diffusion theories, which is in principle advantageous from the performance point of view.  The quasi-ballistic (QB) model predicts 61% and 58% fewer intrinsic channel charges than the saturation velocity model (Vsat) and non-saturation drift velocity model (NVsat), respectively (Figure 1).  The difference diminishes in the linear region or because the device essentially operates with low carrier velocity and a lot of scattering with low V_gs or V_ds.   It is also shown that the benefits of fast carrier transport in tight-pitch logic circuits diminish due to the presence of extrinsic charges, particularly at higher fan-outs. As shown in Figure 2, the stage delay of a 5-stage ring oscillator predicted by QB model is only 5% and 3% less than that by Vsat and Nsat models, respectively. However, for RF applications the benefit of quasi-ballisticity in Si or near-full ballisticity in III-V HEMTs calculated by the model can be significant.



Figure 1: Channel charges associated with the gate terminal under different charge models without extrinsic capacitances. QB model predicts a 61% and 58% less intrinsic channel charge than Vsat and NVsat models at V_ds=V_gs=1V, respectively.



Figure 2: Stage delay of a 5-stage ring oscillator with different charge models. QB model predicts only a 5% and 3% less delay than Vsat and NVsat models, respectively.




1. A. Khakifirooz, O. Nayfeh, and D. Antoniadis, “A simple semiempirical short-channel MOSFET current-voltage model continuous across all regions of operation and employing only physical parameters,” IEEE Transactions on Electron Devices,, vol. 56, pp. 1674-1680, 2009. [↩]
2. L. Wei, O. Mysore, and D. Antoniadis, “Virtual-source based self-consistent charge and transport models for near-ballistic FETs,” to be submitted to 2011 International Electron Devices Meeting. [↩]

Dimitri A. Antoniadis

• Title: Ray and Maria Stata Professor of Electrical Engineering
• Department: Department of Electrical Engineering and Computer Science

Collaborators

• J. L. Hoyt, EECS
• T. Palacios, EECS
• J. del Alamo, EECS
• E. A. Fitzgerald, DMSE
• T. Equi, FCRP Materials, Structures, and Devices Focus Center, Executive Director
• Chang-Hyun Lee, Visiting Scientists, Samsung Semiconductor

Postdoctoral Associate

• L. Wei, Post Doctoral Fellow

Graduate Students

• J. Teherani, Res. Asst., EECS
• J. Lin, Res. Asst., EECS
• E. Polyzoeva, Res. Asst. EECS

Support Staff

• W. Rokui, Admin. Asst. II

Publications

D. A. Antoniadis; “ Nanoelectronics Challenges for the 21st Century,” 23rd International Conference on VLSI Design, Bangalore, India, January 2010. (Keynote speaker).

D. A. Antoniadis; “Nanoelectronics Challenges for the 21^st Century,” Design, Automation, and Test in Europe, DATE 2010, (Keynote speaker).

Kim, D.-H.; del Alamo, J.A.; Antoniadis, D.A.; Brar, B.; “Extraction of virtual-source injection velocity in sub-100 nm III–V HFETs,” International Electron Devices Meeting (IEDM), 2009

P. Hashemi, M. Kim, J. Hennessy, L. Gomez, D. A. Antoniadis, and J. L.Hoyt; “Width-dependent hole mobility in top-down fabricated Si-core/Ge-shell nanowire metal-oxide-semiconductor-field-effect-transistors”, Applied Physics Letters, Vol. 96, pp. 063109-063109-3, 2010.

B. S. Ong, K. L. Pey, C. Y. Ong, C. S. Tan, C. L. Gan, H. Cai, D. A. Antoniadis, and E. A. Fitzgeral; “Effect of Using Chemical Vapor Deposition WSi2 and Postmetallization Annealing on GaAs Metal-Oxide- Semiconductor Capacitors,” Electrochem. Solid-State Lett. 13, H328 (2010)

J. Luo, L. Wei, F. Boeuf, D. Antoniadis, T. Skotnicki, and H.-S. P. Wong, “Device Engineering for  Improving SRAM Static Noise Margin,” 2010 International Conference on Solid State Devices and Materials (SSDM 2010), paper C-4-3, Tokyo, Japan, September  22 – 24, 2010.

Compact Physical Modeling of Graphene Field Effect Transistors

• Authors: H. Wang, A. Hsu, J. Kong, D. A. Antoniadis, T. Palacios
• Sponsorship: SRC/FCRP MSD, ONR GATE MURI Program

Graphene is a two-dimensional (2D) material that has attracted great interest for electronic devices since the demonstration of field effect carrier modulation in 2004 ^[1] . Its high mobility and high saturation velocity make graphene a promising material for next generation of high-frequency devices ^[2] , and its 2D geometry also makes it highly compatible with existing fabrication technology in the semiconductor industry. Furthermore, the possibility of large-scale synthesis of graphene by chemical vapor deposition (CVD) and epitaxial growth ^{[3] [4] [5]} makes graphene integrated circuits a feasible reality in the near future. Hence, it is desirable to develop a compact physical model that can enable the use of computer-aided-design software to simulate future complex circuits. In this work, we develop a compact model for the current-voltage characteristics of graphene field effect transistors (GFETs), which is based on an extension of the “virtual-source” model previously proposed for Si MOSFETs ^{[6] [7]} and is valid for both saturation and non-saturation regions of device operation (Figure 1). This virtual source model provides a simple and intuitive understanding of carrier transport in GFETs, allowing extraction of the virtual source injection velocity v_VS, a physical parameter with great technological significance for short-channel graphene transistors. With only a small set of fitting parameters, the model shows excellent agreement with experimental data (Figure 2). It is also shown that the extracted virtual source carrier injection velocity for graphene devices is much higher than in Si MOSFETs and state-of-the-art III-V HFETs with similar gate length, supporting the great potential of GFETs for high frequency applications. Future work includes extending the model for both small signal and large signal modeling of GFETs RF performance and implementation in Verilog to enable modeling of graphene circuits.



Figure 1: Schematic diagram of the cross-section of a GFET device. The virtual electron source (VES) point and the virtual hole source (VHS) point in the channel are defined for a GFET. The electrostatic potential along the channel and the position of VES and VHS are shown for a GFET operating in the three operating regions: I. Electron conduction region; II. Ambipolar region; III. Hole conduction region.



Figure 2: (a) Top-view of the three-dimensional plot of I_DS vs. V_TGS and V_BGS at V_DS=1.1 V. (b), (c) and (d) are cross-sections in (a) at the corresponding dotted lines. The model results are shown as solid lines; the experiment data is shown as dots. In (b), V_BGS is kept constant at 0 V, and V_TGS is swept from -1 V to 3 V. A family of curves is shown for VDS increasing from 0.35 V to 1.1 V in steps of 0.25 V. In (c), V_TGS is kept constant at 0 V, and V_BGS is swept from -50 V to 100 V. (d) V_TGS is kept constant at 1.41 V, and V_BGS is swept from -30 V to 40 V. A family of curves is shown for V_DS, increasing from 0.35 V to 1.1 V in steps of 0.25 V.




1. K. S. Novoselov, et al., “Electric field effect in atomically thin carbon films,” Science, vol. 306, pp. 666-669, Oct. 2004. [↩]
2. T. Palacios, et al. “Applications of graphene devices in RF communications,” IEEE Comm. Mag., vol. 48,  no. 6, pp. 122-128, June 2010. [↩]
3. A. Reina, et al., “Large area few-layer graphene films on arbitrary substrates by Chemical Vapor Deposition,” Nano Lett., vol. 9, no. 1, pp. 30-35, Jan. 2009. [↩]
4. X. Li, et al. “Large-area synthesis of high-quality and uniform graphene films on copper foils,” Science, vol. 324. no. 5932, June 2009. [↩]
5. C. Berger, et al. “Electronic confinement and coherence in patterned epitaxial graphene,” Science, vol. 312. no. 5777, May 2006. [↩]
6. A. Khakifirooz, O. M. Nayfeh, and D. Antoniadis “A simple semiempirical short-channel MOSFET current-voltage model dontinuous across all regions of operation and employing only physical parameters,” IEEE Trans. Electron Devices, vol. 56, no. 8, Aug. 2009. [↩]
7. D. A. Antoniadis, I. Åberg, C. N. Chleirigh, O. M. Nayfeh, A. Khakifirooz, and J. L. Hoyt, “Continuous MOSFET performance increase with device scaling: The role of strain and channel material innovation,” IBM J. Res. Develop., vol. 50, no. 4/5, pp. 363–376, July 2006. [↩]

Valence Band Offset Extraction Between Strained-Si and Strained-Ge Layers

• Authors: J. T. Teherani, D. A. Antoniadis, J. L. Hoyt
• Sponsorship: NDSEG Fellowship, DARPA, NSF

The type-II band alignment between strained-silicon (s-Si) and strained-germanium (s-Ge) has been proposed for use in tunneling transistors due to the small effective band gap between the s-Si conduction band and s-Ge valence band ^[1] . The small effective band gap may substantially increase tunneling current compared to a Ge homostructure while maintaining low off-state leakage. However, the valence band alignment between thin layers of s-Si and s-Ge on a relaxed SiGe substrate has not been experimentally extracted.

The experimental device structure consists of an Al₂O₃ high-κ dielectric (~6 nm) on a Si capping layer (~ 6 nm) on s-Ge (~ 6 nm) grown pseudomorphically on a relaxed SiGe buffer (~1 µm) with 40% Ge concentration. The wafers were processed into MOS-capacitors and measured using low-frequency and quasistatic C-V techniques. The valence band offset can be extracted by fitting the simulation data to experimental C-V measurements ^[2] . In Figure 1, the width of region II is dependent on the valence band offset and effective band gap between the s-Si and s-Ge layers.

Figure 2 shows the band structure and hole density as a function of position for the fabricated structure. At 0 V gate voltage, most holes near the surface of the capacitor are contained in the s-Ge quantum well. Since the s-Ge quantum well is displaced from the Al₂O₃ surface by the s-Si layer, the effective thickness is larger and thus the measured capacitance is lower than the oxide capacitance. As a more negative bias is applied to the gate, holes begin to accumulate at the s-Si/Al₂O₃ surface so that the total capacitance increases and approaches the oxide capacitance. The extracted valence band offset between the s-Si and s-Ge layers was 740±30 meV, which also suggests a small effective band gap.



Figure 1: C-V curve of experimental and simulation data of the structure shown in Figure 2. The simulation data is fitted by adjusting the valence offset and effective band gap between the s-Si and s-Ge layers. Regions I, II, III, and IV correspond to hole accumulation in the s-Si, hole accumulation in the s-Ge, hole depletion from the s-Ge, and electron inversion in the s-Si, respectively.



Figure 2: The blue lines represent the band structure, and the red lines indicate the hole density as a function of position for the fabricated devices. The dashed lines show values at V_G = -2 V, and solid lines show values at V_G = 0 V. The text labels at the top of the plot indicate the different materials




1. O. M. Nayfeh, C. N. Chleirigh, J. Hennessy, L. Gomez, J. L. Hoyt, and D. A. Antoniadis, “Design of tunneling field-effect transistors using strained-silicon/strained-germanium Type-II staggered heterojunctions,” IEEE Electron Device Letters, vol. 29, no. 9, pp. 1074-1077, Sep. 2008. [↩]
2. C. N. Chleirigh, C. Jungemann, J. Jung, O. O. Olubuyide, and J. L. Hoyt, “Extraction of band offsets in strained Si/strained Si1-yGey on relaxed Si1-xGex dual-channel enhanced mobility structures,” in Proc. Electrochemical Society: SiGe: Materials, Processing and Devices, pp. 99–109, 2005. [↩]

Energy-delay Trade-off for Devices with Asymmetric n-type and p-type Current Drives from a Static-CMOS Circuit-level Perspective

• Authors: L. Wei, D. A. Antoniadis
• Sponsorship: SRC/FCRP MSD, DARPA

Historically, digital logic devices are benchmarked by the on-state current (I_on) at specified off-state current (I_off) and supply voltage (V_dd) at each technology node.  Emerging device technologies are often targeted to outperform Si MOSFETs at the same I_off and V_dd.  Some emerging technologies, such as III-V transistors and Ge transistors, have great advantages in either n-type or p-type devices, instead of both types, at the device level in terms of I_on.  However, recent work [1] shows that devices optimized based on the conventional device-level I_on methodology may not necessarily give the best performance at the circuit-level.  In this work, we extend the methodology proposed in  ^[1] to study the technologies with asymmetric n-type and p-type driving capabilities from a circuit-level perspective.

Circuit-level delay and energy are calculated following the strategies described in ^[1] , assuming static CMOS logic gates.  The smaller of the widths of nMOS (W_n) and pMOS (W_p) is fixed to be 1 mm. Assuming the same pull-up and pull-down delay, the P/N ratio (k=W_p/W_n), is adjusted according to the on-current.   Figure 1(a) minimizes energy per switch at each delay point for selected P/N ratio, with a pMOS and nMOS transporting 10x and 1x current of the 11-nm projection device in ^[1] at the same bias.   The corresponding dynamic energy (E_dyn­) over total energy (E_tot) is shown in Figure 1(b).   It is shown that the optimal sizing ratio is not necessarily 1/10 as in following the conventional sizing scheme.  In fact, the optimal k is the smallest number that can maintain E_dyn at around 80% of E_tot.  As Figure 2 shows, compared with the baseline technology with symmetric nMOS and pMOS, the technology that improves the transport capability of only one type of devices hardly benefits the circuit-level energy-delay trade-off.




Figure 1: (a) Minimum energy per switch and the corresponding (b) E_dyn/E_tot for a circuit application, assuming static-CMOS logic, with a logic depth of 20 and activity factor of 0.01, at selected P/N ratios. The pMOS and nMOS transporting 10x and 1x current of the 11-nm projection device in ^[1] at the same bias. When the penalty of static leakage power, which is proportional to I_off, increases to assure the driving speed, i.e., E_dyn/E_tot decreases to be much less than 80%, the size of the weaker transistor should be increased to suppress the penalty.



Figure 2: The minimum energy per switch as a function of delay, with k as a free variable, for technologies with different strengths of nMOS and pMOS with the 11-nm ITRS projection in ^[1] as the nominal technology.




1. L. Wei, S. Oh, and H. –S. Philip Wong, “Performance benchmarks for Si, III-V, TFET, and carbon nanotube FET – Re-thinking the technology assessment methodology for complementary logic applications,” 2010 IEEE International Electron Devices Meeting, pp. 16.2.1-16.2.4, San Francisco, CA, Dec. 2010 [↩] [↩] [↩] [↩] [↩]

Hole Mobility in Strained-Ge p-MOSFETs with High-k/Metal Gate Stack

• Authors: E. A. Polyzoeva, J. L. Hoyt, D. A. Antoniadis
• Sponsorship: SRC/FCRP MSD

The need for high speed and density in modern integrated circuits requires new MOSFET channel materials, techniques for improved carrier transport, and continuous scaling of the device dimensions. Strained-Ge is implemented in this work as a material for enhanced hole transport.  A high-k dielectric and metal gate stack is used for improved electrostatic control. At present, incorporating an epitaxial Si capping layer between the high-k dielectric and the Ge is the most promising approach for achieving a high quality Ge-dielectric interface, with 10x hole mobility enhancement relative to Si control devices reported for p-MOSFETs using this approach ^[1] .  However, the use of a Si-cap leads to increased Capacitance Equivalent Thickness (CET) of the structure, which degrades electrostatic control.  In addition, a Si cap provides a parasitic path for hole transport, which can deteriorate the effective hole mobility of the device at high inversion charge densities. Therefore, a process to fabricate MOSFETs by depositing a high-k dielectric directly on strained-Ge substrate should be developed and is the aim of this research.

Strained-Ge MOSFETs with and without a Si-cap were fabricated to quantitatively assess the hole mobility and its dependence on dielectric interface quality. The gate stack for all the devices was 6-nm Al₂O₃/30 nm WN.  Figure 1 shows the I-V characteristics of a strained-Ge MOSFET without a Si cap with the device cross-section shown in the inset. A very respectable on-to-off ratio is demonstrated for this long-channel (20-µm) device.  Figure 2 shows the hole mobility for the devices with and without a silicon cap, compared to the universal mobility and previous results reported by Weber et al ^[2] . The samples without a silicon cap showed relatively high hysteresis (~150 mV) and lower hole mobility than the Si-capped devices. However, the mobility enhancement observed for the sample without the Si cap is larger than reported values for relaxed or strained Ge without a Si cap ^{[3] [4]} .  This result is promising and illustrates the need for continued investigation of methods for improved passivation of the strained-Ge surface prior to direct high-k dielectric deposition.



Figure 1: I-V characteristics of a strained-Ge MOSFET without a silicon cap showing 200-mV hysteresis, suggesting some trapping mechanism still exists in the dielectric. The inset shows the cross-section of the device.



Figure 2: Extracted hole mobility for the strained-Ge devices with and without Si cap. The enhancement factor compared to universal hole mobility curve is shown in the figure. The mobility of a previously reported device with a structure 3nm Si/7nm Ge and a HfO2/TiN gate stack is also shown for reference.




1. M. L. Lee and E. A. Fitzgerald, “Optimized strained Si/strained ge dual-channel heterostructures for high mobility P- and N-MOSFETs,” IEDM Technical Digest, vol. 18, no. 1, pp. 1-4, 2003. [↩]
2. O. Weber, Y. Bogumilowicz, T. Ernst, J.-M. Hartmann, F. Ducroquet, F. Andrieu, C. Dupre, L. Clavelier, C. Le Royer, N. Cherkashin, M. Hytch, D. Rouchon, H. Dansas, A.-M. Papon, V. Carron, C. Tabone, and S. Deleonibus, “Strained Si and Ge MOSFETs with high-k/metal gate stack for high mobility dual channel CMOS,” in Electron Devices Meeting, 2005, pp. 137-140. [↩]
3. A. Ritenour, S. Yu, M. L. Lee, N. Lu, W. Bai, A. Pitera, E. A. Fitzgerald, D. L. Kwong, and D. A. Antoniadis, “Epitaxial strained germanium p-MOSFETs with HfO₂ gate dielectric and TaN gate electrode,” IEDM ’03 Technical Digest, vol. 18, no. 2., pp. 1-4. [↩]
4. J. Hennessy, “High mobility germanium MOSFETs: Study of ozone surface passivation and n-type dopant channel implants combined with ALD dielectrics,” Ph.D. Thesis, MIT, Cambridge, 2010. [↩]

Circuit Simulation Using a Verilog-A Implementation of the Virtual-source Transistor Model

• Authors: O. Mysore, D. A. Antoniadis, L. Daniel
• Sponsorship: SRC/FCRP MSD

A variety of compact MOSFET models are used for circuit simulation in both industry and academia, ranging from standard industrial models with dimensional and processing parameter dependencies ^[1] to simple, intuitive physical transport models. The virtual-source model (VS model), a recently developed, simple, semi-empirical, short channel MOSFET model, captures the essential physics with relatively few physical parameters, most of which can be directly determined from device measurements or simulations ^[2] .  Because of its accuracy, simplicity, and scalability, the VS model is excellent for technology benchmarking, performance projection and variability analysis.



Figure 1: Waveform of ring oscillator node voltages.

Previous work on this project involved the implementation of the VS model, including intrinsic charges, in a commercial simulator using Verilog-A, an analog descriptive language.  Commercial circuit simulators allow users to create Verilog-A behavioral modules, which specify the relationships between currents and voltages of the internal and external nodes of the module.  Using such a module, the VS model, including intrinsic charges, was implemented in Verilog-A.  This project uses the Verilog-A implementation of the model to simulate a number of circuits.

Circuits such as ring oscillators, adders, and FIR-filters were simulated in commercial simulators using the Verilog-A implementation of the VS model.  Ring oscillators ranging from fan-out one to seven were implemented, and the delays were compared to experimental data from fabricated ring oscillators.  For the ring oscillators, the appropriate VS model parameters were extracted from measured data, and the parameters were varied in simulations in order to obtain sensitivity analyses.  The node voltages of a fivestage ring oscillator are shown in Figure 1.  For larger circuits, such as an FIR-filter, when convergence difficulties arose, smoothing functions substantially improve convergence.  Based on the circuits implemented as part of this project, using Verilog-A modules in commercial simulators is an adequate method of simulating circuits with the VS model.

1. C. Hu. “BSIM.” Internet: http://www-device.eecs.berkeley.edu/~bsim3/bsim4.html [June 31, 2009]. [↩]
2. A. Khakifirooz, “A simple semiempirical short-channel MOSFET current-voltage model continuous across all regions of operation and employing only physical parameters,” IEEE Transactions on Electron Devices, vol. 56, pp. 1674-1680, 2009. [↩]

A Self-aligned InGaAs Quantum-well Field-effect Transistor for Logic Applications

• Authors: J. Lin, J. A. del Alamo, D. A. Antoniadis
• Sponsorship: Sponsorship: SRC/FCRP MSD

InGaAs is a promising candidate for channel material for future high-performance CMOS logic applications because of its superior electron transport properties ^[1] . InGaAs quantum-well metal-oxide-semiconductor field-effect transistor (QW-MOSFET) research has recently attracted great interest from the IC device community.  N-channel InGaAs-based High-electron-mobility transistors (HEMTs) fabricated previously at MIT have served as an excellent testbed with which to explore issues of importance in a future III-V CMOS technology. They demonstrated outstanding logic device characteristics due to the high injection velocity at low supply voltage and high electrostatic integrity afforded by the quantum-well channel ^{[1] [2] [3]} . These advantages, if ported over to InGaAs MOSFETs, can eventually lead to integrated circuits exhibiting high speed with reduced power dissipation.

There are many challenges in the development of a InGaAs QW-MOSFET technology for future CMOS applications. For example, low series resistance and a compact footprint are required. In this work we prototype a novel self-aligned InGaAs QW-MOSFET that can address these problems. The cross-sectional schematic of the QW-MOSFET is shown in Figure 1. This device uses a thin Al₂O₃ gate dielectric. Molybdenum-based ohmic contacts are self-aligned to the gate. This self-alignment scheme reduces the spacing between the contacts and the gate and leads to a lower series resistance. A first working prototype QW-MOSFET with L_g =2 mm has been fabricated, and the output characteristics are shown in Figure 2. Process optimization, aimed at a further reduction in the source resistance, is being carried out. The scaling behavior and performance analysis with respect to silicon technology for this new device structure will be investigated.



Figure 1: Cross-sectional schematic of self-aligned InGaAs QW-MOSFET.



Figure 2: Output characteristics of a prototype QW-MOSFET with L_g =2 μm.




1. D.-H. Kim, J. A. del Alamo, D. A. Antoniadis, and B. Brar, “Extraction of virtual-source injection velocity in sub-100 nm III-V HFETs,” in IEDM Tech. Dig., pp. 861-864, Dec. 2009. [↩] [↩]
2. D.-H. Kim and J. A. del Alamo, “30 nm E-mode InAs PHEMTs for THz and future logic applications,” in IEDM Tech. Dig., pp. 719-722, Dec. 2008 [↩]
3. T.-W., Kim, D.-H. Kim, and J. A. del Alamo, “Logic characteristics of 40 nm thin-channel InAs HEMTs,” 22nd International Conference on Indium Phosphide and Related Materials, pp. 496-499, May 2010. [↩]