All entries for vladimir stojanovic

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Photonic Processor-DRAM Interface

• Authors: Y.-H. Chen, C. Sun, B. R. Moss, M. Georgas, J. Leu, J. Orcutt, Y. Lee, M. Planas, J. Shainline, K. Mehta, J. Sun, H. Li, E. Timurdogan, S. Urosevic, J. Wang, M. Weaver, K. Asanović, M. Watts, M. Popović, R. Ram, V. Stojanović
• Sponsorship: CICS, DARPA, NSF, SRC/FCRP IFC, Trusted Foundry, Natural Sciences and Engineering Research Council of Canada

Integrated photonic interconnects enable new possibilities for bandwidth and energy-efficiency driven VLSI applications, such as many-core processor systems, by removing the perennial memory bandwidth bottleneck^[1]. Though both heterogeneous^[2][3][4] and monolithic^[5] electronic-photonic platforms have been proposed, monolithic integration remains the preferred choice due to lower interface parasitics and manufacturing costs.

This work will demonstrate an optical processor-memory platform, as shown in the block diagram of Figure 1, which consists of two chips fabricated in two different processes. The DRAM memory chip, implemented in a quarter-micron-equivalent CMOS bulk process, contains both single-wavelength link and wavelength-division multiplexing (WDM) link test sites, called a Megacell. The processor chip, manufactured on a commercial 45-nm SOI process, features a custom vector processor that can use the on-chip WDM link Megacell structure to optically communicate to an emulated DRAM structure. Both chips monolithically integrate photonic link components (vertical grating couplers, ring filters, modulators, and photodiodes) with drivers and synthesized backend circuitry. For link characterization, each Megacell, as shown in Figure 2, contains on-chip pseudorandom binary sequence (PRBS) data generators to feed modulators as well as a bit-error-rate (BER) check receiver backend. Programmable thermal tuning controllers were also added to compensate for process and thermal-induced mismatches in ring resonant devices.



Figure 1: The processor-DRAM interface platform, which consists of a DRAM memory chip and a processor chip with an on-chip Megacell structure and off-chip optical links.



Figure 2: A single transceiver site of the Megacell structure in the DRAM memory chip. The generated PRBS data is modulated through the link and then BER-checked at the receiver side.




1. S. Beamer, C. Sun, Y-J. Kwon, A. Joshi, C. Batten, V. Stojanović, and K. Asanović, ”Re-architecting DRAM with Monolithically Integrated Silicon Photonics,” Int’l Symposium on Computer Architecture (ISCA-37), pp. 129-140, June 2010. [↩]
2. I. Young, E. Mohammed, J. Liao, A. Kern, S. Palermo, B. Block, M. Reshotko, and P. Chang, “Optical I/O technology for tera-scale computing,” IEEE International Solid-State Circuits Conference – Digest of Technical Papers, pp.468-469,469a, Feb. 2009. [↩]
3. A. Rylyakov, C. Schow, B. Lee, W. Green, J. Van Campenhout, Y. Min, F. Doany, S. Assefa, C. Jahnes, J. Kash, and Y. Vlasov,” A 3.9ns 8.9mW 4×4 silicon photonic switch hybrid integrated with CMOS driver,” IEEE International Solid-State Circuits Conference – Digest of Technical Papers, pp. 222-224, Feb. 2011. [↩]
4. F. Liu, D. Patil, J. Lexau, P. Amberg, M. Dayringer, J. Gainsley, H. Moghadam, X. Zheng, J. Cunningham, A. Krishnamoorthy, E. Alon, and R. Ho, “10 Gbps, 530 fJ/b optical transceiver circuits in 40 nm CMOS,” IEEE Symposium on VLSI Circuits, pp. 290-291, June 2011. [↩]
5. J. Orcutt, B. Moss, C. Sun, J. Leu, M. Georgas, J. Shainline, E. Zgraggen, H. Li, J. Sun, M. Weaver, S. Urošević, M. Popović, R. J. Ram, and V. Stojanović, “Open foundry platform for high-performance electronic-photonic integration,” Optics Express, vol. 20, no. 11, pp. 12222-12232, May 2012. [↩]

Designing Complex Digital Systems with Scaled Nano-electro-mechanical Relays

• Authors: H. Fariborzi, F. Chen, R. Nathanael, J. Jeon, L. Hutin, T. K. Liu, V. Stojanović
• Sponsorship: DARPA, CICS, SRC/FCRP C2S2, SRC/FCRP MSD

Silicon CMOS circuits have a well-defined lower limit on their achievable energy efficiency due to sub-threshold leakage. Once this limit is reached, power constrained applications will face a cap on their maximum throughput independent of their level of parallelism. Avoiding this roadblock requires an alternative device with a steeper sub-threshold slope, i.e., lower V_DD/I_on for the same I_on/I_off. One promising class of such devices is electrostatically actuated nano-electro-mechanical (NEM) switches with nearly ideal I_on/I_off characteristics. Although mechanical movement makes NEM switches significantly slower than CMOS, they can be useful for a wide range of VLSI applications if we reexamine traditional system- and circuit-level design techniques to take advantage of the electrical properties of the device.

Basic circuit design techniques and functionality of some main building blocks of VLSI systems, such as logic, memory, and clocking structures, have been demonstrated in our previous works^[1][2][3]. Recently, by employing pass-transistor logic design, we have designed and demonstrated complex relay-based arithmetic units such as multipliers (Figure 1b-c)^[4]. Simulation results of an optimized 16-bit relay multiplier built in a 90-nm equivalent relay process model predict ~10x improvement in energy-efficiency over optimized CMOS designs in the 10-100 MOPS performance range. The relative performance of the multiplier enhancements are in line with what was previously predicted by a NEM relay 32-bit adder^[3], suggesting that complete VLSI systems, such as a microprocessor, would expect to see similar energy/performance improvements from adopting NEM relay technology^[3],^[4].

Since scaling is crucial for performance, energy, and total area improvement, we have developed a scaled version of the original relay, a 6-terminal relay, which is 25x smaller and offers enhanced functionality. The operation of the main building block of the NEM-relay based multiplier, the (7:3) compressor, built with these scaled devices is experimentally demonstrated. This circuit, consisting of 46 scaled relays, is the largest scaled relay circuit successfully tested to date (Figure 2).



Figure 1: (a) The 4T NEM relay and its operating states, (b) a 6-bit relay multiplier built with full and half adders, and (c) an alternative design built with (7:3) and smaller compressors.



Figure 2: (a) The original 4T and the scaled 6T devices and their symbols, (b) the MSB sub-circuit of the (7:3) compressor and the updated topology for the 6T relay, and (c) experimental results of the full 6T compressor.




1. F. Chen, M. Spencer, R. Nathanael, C. Wang, H. Fariborzi, A. Gupta, H. Kam, V. Pott, J. Jeon, T. K. Liu, D. Marković, V. Stojanović, and E. Alon, “Demonstration of Integrated Micro-electro-mechanical Switch Circuits for VLSI Applications,” IEEE International Solid-State Circuits Conference Technical Digest, Feb. 2010, pp. 150-151. [↩]
2. H. Fariborzi, M. Spencer, V. Karkare, J. Jeon, R. Nathanael, C. Wang, F. Chen, H. Kam, V. Pott, T. K. Liu, E. Alon, V. Stojanović, and D. Marković, “Analysis and Demonstration of MEM-relay Power Gating,” presented at IEEE Custom Integrated Circuits Conference, San Jose, CA, 2010. [↩]
3. M. Spencer, F. Chen, C. C. Wang, R. Nathanael, H. Fariborzi, A. Gupta, H. Kam, V. Pott, J. Jeon, T. K. Liu, D. Marković, E. Alon, and V. Stojanović, “Demonstration of Integrated Micro-electro-mechanical Relay Circuits for VLSI Applications,” IEEE Journal of Solid State Circuits, Jan. 2011. [↩] [↩] [↩]
4. H. Fariborzi, F. Chen, R. Nathanael, J. Jeon, T.K. Liu, and V. Stojanović, “Design and Demonstration of Micro-electro-mechanical Relay Multipliers,” presented at IEEE Asian Solid State Circuit Conference, Jeju, S. Korea, 2011. [↩] [↩]

Erbium Silicon Photonic Integrated Oscillators and Radar (ESPIOR)

• Authors: J. Leu, B. Moss, C. Sun, M. Georges, Y. Chen, D. Yost, M. Watts, V. Stojanovic
• Sponsorship: DARPA

A novel device, erbium silicon photonic integrated oscillators and radar (ESPIOR), is composed of state-of-the-art silicon photonics and erbium-ytterbium based laser oscillators, integrated onto a CMOS wafer with 1fF capacitance 3D vias^[1], in conjunction with hybrid attached optical components including a pump laser, an optical isolator, and a saturable absorber. ESPIOR uses a unique combination of a low phase noise continuous-wave (CW) distributed feedback (DFB) laser master oscillator, and a mode-locked laser (MLL) frequency divider to achieve a low phase noise 20-GHz microwave carrier. A schematic of the complete system is shown in figure 1.

To implement the design across the photonic wafer and CMOS wafer, a merged design environment was created. Photonic devices were drawn as parameterized cells and then treated as macro blocks that could be placed throughout the chip using scripts. For verification, design rules were added to ensure the manufacturing yield of the 3D vias that connect the circuits with the photonic devices. Layout-vs-schematic (LVS) rules were used to compare the netlist including photonic components to the integrated layout, where each contact of the photonic devices was labeled.

To test the individual photonic/electric building blocks of the ESPIOR, we have test sites for photodiodes connected with transimpedance amplifiers, linear modulators and phase shifters connected to driver circuits, switches, lasers, etc. Many combinations of design types were implemented, enabling us to test the performance tradeoffs in various designs. For instance, the driver circuit for the linear modulator was designed at different bandwidth specifications. Also, the modulator itself has travelling wave vs. lumped capacitance variants. As a demonstration of the integrated platform separate from the ESPIOR, a digital CMOS section was implemented; in it, many modulators, switches and photodiodes are connected in various link configurations. The analog CMOS transmitter and receiver frontends are highly configurable and can perform on-chip bit-error-rate testing.



Figure 1: A diagram of the ESPIOR oscillator, which utilizes the low phase noise properties of a continuous-wave laser as a master oscillator and a mode-locked laser as a frequency divider.

1. C. L. Chen, D.-R. Yost, et al., “Wafer-scale 3D integration of InGaAs photodiode arrays with Si readout circuits by oxide bonding and through-oxide vias,” Microelectronic Engineering, vol. 88, no. 1, Jan. 2011. [↩]

Building Compressed Sensing Systems

• Authors: O. Abari, F. Chen, F. Lim, A. Chandrakasan, V. Stojanović
• Sponsorship: NSF, Natural Sciences and Engineering Research Council of Canada

Compressed sensing (CS) is a sub-Nyquist sampling technique^[1] with under-explored implementation potential. In this multi-disciplinary project, we analyze CS circuit architectures from a hardware implementation perspective^[2],^[3], develop and apply end-to-end evaluation methodologies from a system perspective^[4],^[5], and support experiments by analyses from a theoretical perspective^[6]. We have considered the practical aspects of CS applied to both wireless sensors and Analog Information Converters (AICs).  For the former, we showed that a digital CS-based sensor system is efficient and robust. By data compression alone, CS enables over 10X energy reduction in transmission energy; see Figure 1. CS is robust to channel errors, and amenable to simple schemes to enable 4X energy reduction^[4]. For the latter (AICs), we evaluated the ability of CS to overcome resolution/performance limitations of Nyquist-rate high-speed sampling (limited by jitter, aperture and other circuit impairments). We find AICs have no performance advantage over high-speed ADCs. In standard architectures, signal encoding is realized with a mixer-like circuit, which still operates at Nyquist frequency to avoid input aliasing. Our evaluation shows that AICs are resolution limited, though they may enable a 2x energy reduction for low amplifier gains and very sparse signals^[5].

There is little literature on CS recovery hardware. As an initial step, we explored the implementation design space for a matching pursuit (MP) algorithm; see Figure 2 (insert)^[7]. We chose MP as it is the simplest possible recovery algorithm, so that we may gain critical first insights. MP is a greedy (iterative) algorithm that estimates a sparse sample in each iteration and produces the full estimate once it halts. The figure also shows the basic implementation blocks where we found that the max-correlation unit, which consists of multipliers, dominates the energy expenditure. The energy-cost evaluation in Figure 2 shows diminishing returns around 20 multipliers, at 1 V supply, in 45-nm CMOS technology.  Overall, at 8 bits resolution and 10 fixed iterations, the energy cost of recovery is 2.8 nJ/sample, with an area of 0.4 mm² at a minimum-energy throughput of 2.5 mega-samples/s at 0.4 V supply. Since the algorithm is block-parallel, a further throughput increase comes with a linear increase in area.



Figure 1: Minimum energy versus percent RMS difference (PRD). Compared average (PRDavg) and worst (PRDnet) distortions, optimized over compression rate (M) and quantization (QCS).



igure 2: Matching pursuit. Energy-cost evaluation finds flattening of minimum energy curve, dominated by multipliers in the correlation block. Nominal 1 V supply, 45-nm process.




1. E. Candes and T. Tao, ”Decoding by Linear Prog.,” IEEE Transactions on Information Theory, vol. 51, no. 12, pp. 4203-4215, Dec. 2005. [↩]
2. F. Chen, A. P. Chandrakasan, and V. Stojanovic, ”Design and Analysis of a Hardware-Efficient Compressed Sensing Architecture for Data Compression in Wireless Sensors” IEEE Journal of Solid-State Circuits, vol. 47, no. 3, pp. 744-756, Mar. 2012. [↩]
3. F. Chen, A. Chandrakasan, V. Stojanovic, and E. Alon, “A Signal-agnostic Compressed Sensing Acquisition System for Wireless and Implantable Sensors,” in Proc. IEEE Custom Integrated Circuits Conference, Sep. 2010. [↩]
4. F. Chen, F. Lim, O. Abari, A. Chandrakasan, and V. Stojanovic, “Energy-Aware Design of Compressed Sensing Sys, for Wireless Sensors under Performance and Reliability Constraints,” IEEE Transactions on Circuits and Systems I, vol. 60, no. 3, pp. 650-661, Mar. 2013. [↩] [↩]
5. O. Salehi-Abari, F. Chen, F. Lim, and V. Stojanovic, “Performance Trade-offs and Design Limitations of Analog-to-Information Converter Front-Ends,” in Proc. IEEE International Conference on Acoustics, Speech and Signal Processing, Kyoto, Japan, Mar. 2012. [↩] [↩]
6. F. Lim and V. Stojanovic, ”U-statistics and Compressed Sensing I: Non-Asymptotic Average-Case Analysis,” IEEE Transactions on Signal Processing, vol. 61, no. 10, pp. 2473-2485, May 2013. [↩]
7. O. Salehi-Abari, “Building Compressed Sensing Systems:  Sensors and Analog-to-Information Converters,” Master’s thesis, Massachusetts Institute of Technology, Cambridge, 2012. [↩]

Beyond Equalization: Model Predictive Control

• Authors: A. Suleiman, R. Sredojević, V. Stojanović
• Sponsorship: Intel

As CMOS technology scales down and the need for higher data rates increases, non-ideal channel characteristics play a critical role in limiting the speed. Equalization is a well-known method to overcome band-limited channels and reflections^[1]. Most high-speed links apply transmitter equalization using a finite impulse response feed forward equalizer (FFE), with an optional decision feedback equalizer (DFE) at the receiver^[2],^[3].

This work proposes a new nonlinear equalization method using a model predictive control (MPC) algorithm.  MPC is a class of control algorithms in which the current control action is obtained by solving online, perhaps approximately, an open-loop optimal control problem. One important advantage of MPC in peak-power constrained link environment is its ability to cope with hard constraints on controls and states^[4]. Figure 1 shows how this algorithm is used; the channel is modeled as an FIR (Figure 1a) filter, which enables feeding back channel states to the MPC controller to solve the optimization problem (Figure 1b). Knowing the state of the channel enables a very fine nonlinear equalization.

MPC equalization significantly outperforms traditional FIR-based equalizers by more than 63% increase in eye opening height as shown in figure 2. Interestingly, the more the channel is dispersed in time and suffers from reflections, the more improvement MPC can achieve. The complexity of this algorithm is the main challenge in implementations; however, techniques can be applied to design hardware MPC equalizers with reasonable area and power budgets, by sacrificing some performance gains. The main candidate is a RAM-DAC implementation^[5], which can achieve equalization and compensate for any timing mismatches or DAC non-linearity.



Figure 1: Modeling the equalization problem: (a) channel state-space representation, (b) block diagram for MPC algorithm. Note that the MPC controller is a function of input bits (horizon) and channel current state.



Figure 2: (a) Pulse response of 3 inches backplane channel @ 8 Gbps^[6] . (b) Channel output with 20-tap FIR equalizer. (c) Channel output with MPC equalizer.




1. J. Liu and X. Lin, “Equalization in high-speed communication systems,” IEEE Circuits and Systems Magazine, vol. 4, no. 2, pp. 4- 17, 2004. [↩]
2. V. Stojanovic and M. Horowitz, “Modeling and analysis of high-speed links,” in Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 589- 594, 2003. [↩]
3. A. Agrawal, J. Bulzacchelli, T. Dickson, Y. Liu, J. Tierno, and D. Friedman, “A 19Gb/s serial link receiver with both 4-tap FFE and 5-tap DFE functions in 45nm SOI CMOS,” in Proceedings of the IEEE International Solid-State Circuits Conference, pp. 134-136, Feb. 2012. [↩]
4. J-S. Zhou, Z-Y. Liu, and R. Pei, “A new nonlinear model predictive control scheme for discrete-time system based on sliding mode control,” Proceedings of the 2001 American Control Conference, vol. 4, pp. 3079-3084, 2001. [↩]
5. R. Sredojević and V. Stojanović, “Fully Digital Transmit Equalizer With Dynamic Impedance Modulation,” IEEE Journal of Solid-State Circuits, vol. 46, no. 8, pp. 1857-1869, Aug. 2011. [↩]
6. W. Peters, E. Gong, C. Chen, and H. Kim, “Improved HVM ATCA measurement data,” http://www.ieee802.org/3/ap/public/channel_model/peters_m1_0605.zip, July 2005. [↩]

Integrated Microring Tuning in Deep-trench Bulk CMOS

• Authors: C. Sun, E. Timurdogan, M. R. Watts, V. Stojanović
• Sponsorship: DARPA, NSF

Wavelength-division multiplexed (WDM) silicon-photonic links form a promising alternative to traditional electrical interconnects. However, the essential component of these WDM networks, the microring resonator, suffers from resonance drifts due to either static process variations or dynamic temperature fluctuations, necessitating methods for active resonance tuning^[1],^[2]. In this work, we demonstrate a heater driver system for microring resonators consisting of a fully-digital Δ∑-based heater driver circuit and an ARM filter (Figure 1, left), both monolithically integrated in a commercial 0.25-µm-equivalent bulk CMOS process with deep-trench isolation capability. Integration of the heater driver alongside the integrated heater minimizes the parasitic resistance from the driver to the heater, provides a digital heater control interface through which multiple rings can be controlled on-chip, and eliminates the dedicated pads for external heater control used in the majority of previous work.

The driver circuit consists of a synthesized pipelined accumulator and a custom one-transistor driver head (Figure 1, right). The circuit utilizes pulse density modulation (PDM) to output a heater drive waveform consisting of a digital pulse train, with a duty-cycle corresponding to an 8-bit digital input setting. The clock frequency of the driver can be used to trade-off the backend power overhead with the size of the digital ripples. The 6-μm diameter ARM filter^[3] is made using Poly-Si waveguides above deep oxide trenches (Figure 1, left) and achieves an uncorrupted free spectral range (FSR) of 3.7THz (Figure 2, left). Using a process-compatible supply voltage of 2.5V, the system is able to tune the resonance by 350GHz, with an efficiency of 10-15µW/GHz (Figure 2, right).



Figure 1: Layout of the integrated heater driver connected to the ARM filter, both integrated in a deep trench CMOS process (left). Block diagram of the Δ∑-based heater driver with SEM of the connected ARM filter (right).



Figure 2: Optical response of the ring filter at minimum and maximum heater power settings (left) and tuning cost per gigahertz, with driver cost included, to reach a specific tuning offset (right).




1. A. Biberman, D. C. Trotter, C. Sun, M. Moresco, V. Stojanović, and M. R. Watts, “Automated wavelength recovery for microring resonators,” in Proc. Conference on Lasers and Electro-Optics, CM2M.1 2012. [↩]
2. M. Georgas, J. Leu, B. Moss, and C. Sun, “Addressing link-level design tradeoffs for integrated photonic interconnects,” Custom Integrated Circuits Conference (CICC), Sept. 2011. [↩]
3. M. R. Watts, “Adiabatic Microring-Resonators,” Optics Letters, vol. 35, no. 19, 2010. [↩]

A Monolithically-integrated Optical Carrier-injection Ring Modulator and All-digital Driver Circuit in Commercial 45-nm SOI

• Authors: B. R. Moss, C. Sun, M. Georgas, J. Shainline, J. S. Orcutt, J. C. Leu, M. Wade, H. Li, R. Ram, M. A. Popović, V. Stojanović
• Sponsorship: DARPA, NSF, SRC/FCRP IFC, Trusted Foundry, CICS, Natural Sciences and Engineering Research Council of Canada

A monolithically integrated photonic modulator and driver circuit is a key building block toward realizing a dense and energy-efficient communication fabric that can satisfy future bandwidth density demands in VLSI systems.

The optical modulator device is a resonant ring with rib waveguide carrier-injection phase shifters, identical to the one in^[1]. The DDR driver in Figure 1 is designed as an all-digital push-pull circuit with configurable drive strengths, sub-bit-time pre-emphasis^[2] and split supplies, operating over a range of drive current profiles required for a wide variety of optical devices. The split power supply and level-shift drivers allow exploration of the tradeoffs between energy-cost and extinction ratio. The highly configurable driver back-end controls four independent drive heads, each providing a configurable drive strength and specialized biasing regime. As illustrated in the Figure 1 inset, a combination of drive segments A and B provides the strongest drive generating the sub-bit current pre-emphasis needed for fast injection of carriers into the modulator on a “0” to “1” transition. Reduced strength segment B maintains the lower current levels necessary for keeping the carriers inside the modulator during a logic “1,” replacing carriers lost in recombination. On a “1” to “0” transition, segment D provides a fast reverse-bias period, enabling carrier discharge from the modulator. After the brief discharge period, the modulator is weakly forward-biased into the subthreshold through segment C, lowering the on-resistance of the modulator intrinsic region and allowing faster turn-on “0” to “1.”  The final drive heads and optical eye diagram are shown in Figure 2. In combination with the forward and reverse-bias sub-bit pre-emphasis, the weak subthreshold forward biasing speeds up the device an order of magnitude above its inherent bandwidth.

The modulator and its driver, operating at 2.5 Gb/s and 1.23 pJ/b with an extinction ratio of 3dB, demonstrate the fastest, most energy-efficient monolithically integrated driver/modulator in sub-100-nm CMOS technology to date.



Figure 1: Modulator and driver circuit fed by an on-chip 32-bit pseudo-random bit sequence generator.



Figure 2: Final driver segments and 2.5 Gb/s eye diagram at 1.23 pJ/b and extinction ratio of 3 dB. An off-chip tunable laser provides the incoming 1550-nm-band light.




1. J. Orcutt, B. Moss, C. Sun, J. Leu, M. Georgas, J. Shainline, E. Zgraggen, H. Li, J. Sun, M. Weaver, S. Urošević, M. Popović, R. J Ram, and V. Stojanović, “Open foundry platform for high-performance electronic-photonic integration,” Optics Express, vol. 20, no. 1, pp. 12222-12232, May 2012. [↩]
2. Q. Xu, S. Manipatruni, B. Schmidt, J. Shakya, and M. Lipson, “12.5 Gbit/s carrier-injection-based silicon micro-ring modulators,” Optics Express vol. 15, pp. 430-436, Jan. 2007. [↩]

Numerical Computation Platform Designed for Optimization

• Authors: R. Sredojevic, A. C. Wright, V. Stojanovic
• Sponsorship: SRC/FCRP C2S2, CICS

Significant effort is spent researching hardware and software acceleration of basic building blocks for numerical computation^[1][2][3]; however, the majority of the previous work focuses on either hardware or software independently. In this work we develop hardware and software together, as shown in Figure 1, providing tight design-time coupling between them, with the ultimate goal of exploring numerical hardware platform tradeoffs at both limits of performance: high speed and low power.

For tight coupling of the algorithm and processor physical layer constraints, our project is centered on the link between these layers: an optimizing compiler. Algorithm optimization begins with synthesizing the computation graph from the written algorithm. Next the graph is optimized through constant folding, dead-code elimination and similar compiler techniques. Additionally tree-rebalancing optimizations are performed to allow for serial associative operations to occur in parallel. Extensive scheduling sweeps are then performed for various processor microarchitectures to find the optimal software/hardware pair. The specifications are fed to an abstract processor template to generate a custom processor similar to the one shown in Figure 2 to run the optimal software. This processor template is written in Bluespec to allow us to postpone decisions on a number of details such as the number and types of processing units, the number and size of memories, the pipeline depths of the floating-point units, and the interconnect structure.

The generated processors are currently synthesized onto a prototyping FPGA platform to confirm our compiler predictions. We see a strong run-time dependence on processor microarchitecture for a given algorithm. Reductions up to 4x in overall latency can be obtained by proper processor configuration, validating a meta-programming approach to processor logic-level design. Furthermore, we show that the optimal latency point is neither at the minimum cycle count nor at the highest clock frequency, but somewhere in between that depends on the topology of the computational flow graph.



Figure 1: The design process for optimized hardware and software for computation applications.



Figure 2: Architecture of a custom numerical computation processor generated by the processor template.




1. J. Mattingley and S. Boyd, “Real-Time Convex Optimization in Signal Processing,” IEEE Signal Processing Magazine, vol. 27, no. 3, pp. 50-61. [↩]
2. K. V. Ling, S. P Yue,. and J. M. Maciejowski, “A FPGA implementation of model predictive control,” 2006 American Control Conference, pp. 1930-1935. [↩]
3. B. Leung, et al., 2010. “An Interior Point Optimization Solver for Real Time Inter-Frame Collision Detection: Exploring Resource-Accuracy-Platform Tradeoffs,” 2010 International Conference on Field Programmable Logic and Applications, pp.113-118. [↩]