Designing Complex Digital Systems with Scaled Nano-electro-mechanical Relays
- Category: Circuits & Systems, MEMS & BioMEMS
- Tags: hossein fariborzi, vladimir stojanovic
Print This Page
Download as PDFSilicon CMOS circuits have a well-defined lower limit on their achievable energy efficiency due to sub-threshold leakage. Once this limit is reached, power constrained applications will face a cap on their maximum throughput independent of their level of parallelism. Avoiding this roadblock requires an alternative device with a steeper sub-threshold slope, i.e., lower VDD/Ion for the same Ion/Ioff. One promising class of such devices is electrostatically actuated nano-electro-mechanical (NEM) switches with nearly ideal Ion/Ioff characteristics. Although mechanical movement makes NEM switches significantly slower than CMOS, they can be useful for a wide range of VLSI applications if we reexamine traditional system- and circuit-level design techniques to take advantage of the electrical properties of the device.
Basic circuit design techniques and functionality of some main building blocks of VLSI systems, such as logic, memory, and clocking structures, have been demonstrated in our previous works[1][2][3]. Recently, by employing pass-transistor logic design, we have designed and demonstrated complex relay-based arithmetic units such as multipliers (Figure 1b-c)[4]. Simulation results of an optimized 16-bit relay multiplier built in a 90-nm equivalent relay process model predict ~10x improvement in energy-efficiency over optimized CMOS designs in the 10-100 MOPS performance range. The relative performance of the multiplier enhancements are in line with what was previously predicted by a NEM relay 32-bit adder[3], suggesting that complete VLSI systems, such as a microprocessor, would expect to see similar energy/performance improvements from adopting NEM relay technology[3],[4].
Since scaling is crucial for performance, energy, and total area improvement, we have developed a scaled version of the original relay, a 6-terminal relay, which is 25x smaller and offers enhanced functionality. The operation of the main building block of the NEM-relay based multiplier, the (7:3) compressor, built with these scaled devices is experimentally demonstrated. This circuit, consisting of 46 scaled relays, is the largest scaled relay circuit successfully tested to date (Figure 2).
-
- Figure 1: (a) The 4T NEM relay and its operating states, (b) a 6-bit relay multiplier built with full and half adders, and (c) an alternative design built with (7:3) and smaller compressors.
-
- Figure 2: (a) The original 4T and the scaled 6T devices and their symbols, (b) the MSB sub-circuit of the (7:3) compressor and the updated topology for the 6T relay, and (c) experimental results of the full 6T compressor.
- F. Chen, M. Spencer, R. Nathanael, C. Wang, H. Fariborzi, A. Gupta, H. Kam, V. Pott, J. Jeon, T. K. Liu, D. Marković, V. Stojanović, and E. Alon, “Demonstration of Integrated Micro-electro-mechanical Switch Circuits for VLSI Applications,” IEEE International Solid-State Circuits Conference Technical Digest, Feb. 2010, pp. 150-151. [↩]
- H. Fariborzi, M. Spencer, V. Karkare, J. Jeon, R. Nathanael, C. Wang, F. Chen, H. Kam, V. Pott, T. K. Liu, E. Alon, V. Stojanović, and D. Marković, “Analysis and Demonstration of MEM-relay Power Gating,” presented at IEEE Custom Integrated Circuits Conference, San Jose, CA, 2010. [↩]
- M. Spencer, F. Chen, C. C. Wang, R. Nathanael, H. Fariborzi, A. Gupta, H. Kam, V. Pott, J. Jeon, T. K. Liu, D. Marković, E. Alon, and V. Stojanović, “Demonstration of Integrated Micro-electro-mechanical Relay Circuits for VLSI Applications,” IEEE Journal of Solid State Circuits, Jan. 2011. [↩] [↩] [↩]
- H. Fariborzi, F. Chen, R. Nathanael, J. Jeon, T.K. Liu, and V. Stojanović, “Design and Demonstration of Micro-electro-mechanical Relay Multipliers,” presented at IEEE Asian Solid State Circuit Conference, Jeju, S. Korea, 2011. [↩] [↩]