All entries for judy l hoyt

• Print This Page
• Download as PDF

Judy L. Hoyt

• Title: Professor
• Department: Department of Electrical Engineering and Computer Science

Collaborators

• Dimitri Antoniadis, EECS
• Eugene Fitzgerald, DMSE
• Pouya Hashemi, IBM
• Ammar Nayfeh, Masdar Institute
• Eli Yablonovitch, UC Berkeley
• Maggie Xia, UBC

Graduate Students

• Winston Chern, EECS
• Eva Polyzoeva, EECS
• Jamie Teherani, EECS (co-super­vised with Prof. Dimitri Antoniadis)
• Tao Yu, EECS
• underGraduate sTUDENTS
• Chen Dan Dong, EECS

Research Staff

• Gary Riggott, Research Specialist

Support Staff

• Loriann McCormick, Administrative Assistant II

Publications

J. T. Teherani, S. Agarwal, E. Ya­blonovitch, J. L. Hoyt, and D. A. Antoniadis, “Impact of Quantization Energy and Gate Leakage in Bi­layer Tunneling Transistors,” IEEE Electron Device Letters, vol. 34, no. 2, pp. 298 –300, Feb. 2013.

W. Chern, P. Hashemi, J.T. Tehe­rani, T. Yu, Y. Dong, G. Xia, D.A. Antoniadis, and J.L. Hoyt, “High Mobility High-κ-All-Around Asym­metrically-Strained Germanium Nanowire Trigate p-MOSFETs”, in IEDM Tech. Dig., 2012, pp. 387-390.

N.A. DiLello, D.K. Johnstone, and J.L. Hoyt, “Characterization of dark current in Ge-on-Si photodiodes,” Journal of Applied Physics, v 112, n 5, p 054506, Sept. 2012.

S.A. Hadi, P. Hashemi, N. DiLello, A. Nayfeh, and J.L.Hoyt, “Thin film a-Si/c-Si1-xGex/c-Si heterojunction solar cells with Ge content up to 56%,”  2012 IEEE 38th Photovol­taic Specialists Conference (PVSC), p 000005-8, 2012.

J.T. Teherani, W. Chern, D.A. An­toniadis, J.L. Hoyt, L. Ruiz, C.D. Poweleit, and J. Menendez, “Ex­traction of large valence-band en­ergy offsets and comparison to theoretical values for strained-Si/strained-Ge type-II heterostruc­tures on relaxed SiGe substrates,” Physical Review B (Condensed Matter and Materials Physics), v 85, n 20, p 205308, 15 May 2012.

S.A. Hadi, P. Hashemi, N. DiLello, A. Nayfeh, and J.L. Hoyt, “Effect of c-Si1-xGex Thickness Grown by LPCVD on the Performance of Thin-Film a-Si/c-Si1-xGex/c-Si Heterojunction Solar Cells”,  MRS Proceedings, Volume 1447, 2012.

P. Hashemi and J.L. Hoyt, “High Hole-Mobility Strained-Ge/Si0.6 Ge0.4 P-MOSFETs With High-K/Metal Gate: Role of Strained-Si Cap Thickness,” IEEE Electron Device Letters, v 33, n 2, p 173-5, Feb. 2012.

S.A. Hadi, A. Nayfeh, P. Hashemi, and J.L. Hoyt, “a-Si/c-Si1-xGex/c-Si heterojunction solar cells,” in International Conference on Sim­ulation of Semiconductor Pro­cesses and Devices, SISPAD, pp. 191-194, 2011.

S.A. Hadi, P. Hashemi, A. Nayfeh, and J.L. Hoyt, “Thin-Film a-Si/c-Si1-xGex/c-Si Heterojunction Solar Cells: Design and Material Quality Requirements,” ECS (Electro­chemical Society) Transactions, Vol. 41 (4), pp. 3-14, 2011.

S. Paydavosi, K. Aidala, P. Brown, P. Hashemi, G. J. Supran, J. L. Hoyt, and V. Bulovic, “High-Den­sity Charge Storage on Molecular Thin Films- Candidate Materials for High Storage Capacity Memory Cells,” IEEE International Electron Device Meeting (IEDM ’11), Washington DC, USA, December 2011.

(Invited) J. Hoyt, P. Hashemi, and W. Chern, “Strained Nanowire MOSFETs,” invited talk presented at the 220th Electrochemical Soci­ety (ECS), Session E9-ULSI Pro­cess Integration, Boston, Massa­chusetts, USA, October 2011.

(Invited) Pouya Hashemi, H.-S. Lee, M. A. Bhuiyan, D. A. Antoni­adis, and J. L. Hoyt,  “High Mobility Strained Ge Channels and Gate Dielectrics for Planar and Non-Planar p-MOSFETs,” Mat. Res. Soc. Meeting, San Francisco, April 27, 2011.

N. A. DiLello and J.L. Hoyt, “Im­pact of post-metallization anneal­ing on Ge-on-Si photodiodes pas­sivated with silicon dioxide,” Appl. Phys. Lett. 99, 033508 (2011).

Khilo, A; Spector, S.J.; Grein, M.E.; Nejadmalayeri, A.H.; Holzwarth, C.W.; Sander, M.Y.; Dahlem, M.S.; Peng, M.Y.; Geis, M.W.; DiLello, N.A.; Yoon, J.U.; Motamedi, A.; Orcutt, J.S.; Wang, J.P.; Sorace-Agaskar, C.M.; Popo­vic, M.A.; Jie Sun; Gui-Rong Zhou; Hyunil Byun; Jian Chen; Hoyt, J.L.; Smith, H.I.; Ram, R.J.; Perrott, M.; Lyszczarz, T.M.; Ippen, E.P.; Kart­ner, F.X, “Photonic ADC: over­coming the bottleneck of electronic jitter”, Optics Express, v 20, n 4, p 4454-69, 21 Nov. 2011.

P. Hashemi, J.T. Teherani, and J.L. Hoyt, “Investigation of Hole Mobility in Gate-All-Around Si Nanowire p-MOSFETs with High-k/Metal-Gate: Effects of Hydrogen Thermal Annealing and Nanowire Shape,” International Electron De­vice Meeting (IEDM 2010), San Francisco, USA, Session 34.5 De­cember 2010.

M. Kim, P. Hashemi, and J.L. Hoyt, “Increased critical thickness for high Ge-content strained SiGe-on-Si using selective epitaxial growth,” Appl. Phys. Lett., 97, 262106 (2010).

Design and Fabrication of a Si Sub-cell for Multi-junction GaAsP/Si Solar Cells

• Authors: E. A. Polyzoeva, S. A. Hadi, E. A. Fitzgerald, A. Nayfeh, J. L. Hoyt
• Sponsorship: MASDAR

This work is part of a collaborative program aimed at ultimately achieving photovoltaic conversion with more than 40% efficiency at a lower cost by combining low-cost manufacturing on large-area Si wafers with high-efficiency III-V materials in a tandem cell. The goal of work described here is to develop a fabrication process for a tandem GaAsP/Si solar cell and silicon sub-cell and to understand the effects of the material quality on the cell performance.  In the initial work, the  focus is on optimizing the base Si cell to achieve the highest possible short-circuit current as it is recognized that the current from the Si sub-cell will most likely be the limiting factor in the overall performance of the tandem cell.

The Si cell process flow and device cross-section are shown in Figure 1. The doping level of the epitaxially-grown Si emitter was varied between 6×10¹⁸ cm^-3 and 2.5×10¹⁹ cm^-3 with a thickness between 0.25 and 1 μm.  An additional 1-μm-thick boron-doped layer was grown prior to emitter growth on one of the wafers to effectively move the PN junction away from the epi-substrate interface and from possible defects. The devices with this layer present showed 10x less leakage current than the devices from wafers with emitters grown directly on the substrate. Maximum EQE of 17% and a short-circuit current density of 34 mA/cm² (at AM1.5) was measured for the cell with emitter doping and thickness of 6×10¹⁸ cm^-3 and 1 μm, respectively.  The I-V characteristics are shown in Figure 2.  Work is in progress on the III-V integration with these baseline Si cells.



Figure 1: Process flow and cross-section of the silicon solar cell.



Figure 2: I-V characteristics of a Si cell with emitter thickness of 1 μm and doping level of 6×10¹⁸ cm-^3, at AM1.5.

 

Fabrication Technology for InGaAs/GaAsSb Vertical Tunnel-FETs

• Authors: T. Yu, J. T. Teherani, J. L. Hoyt
• Sponsorship: NSF Center for Energy Efficient Electronics Science

With the continuing downscaling of the modern complementary metal–oxide–semiconductor (CMOS) technology, integrated circuit power consumption has become one of the most critical issues. This development is due to the limit of operation voltage scaling, which originates from the limit of 60mV/dec sub-threshold swing in the conventional MOS devices^[1]. Various device structures have been proposed to achieve sub-threshold swing below 60mV/dec using novel device physics, including impact ionization^[2], interband tunneling^[3], etc. In particular, tunnel-field-electron transistors (T-FETs) have attracted much attention due to their potential of achieving sharp subthreshold behavior, CMOS compatibility, and scalability^[4]. Vertical T-FETs with a heterojunction structure have been proposed to yield higher tunneling efficiency, and thus larger tunneling current^[4], and are potential candidates for future-generation low-power technology. In this study, InGaAs/GaAsSb heterojunction vertical T-FETs were designed and fabricated to investigate the impacts of different structural parameters.

The cross-sectional view of the InGaAs/GaAsSb vertical T-FET appears in Figure 1. The tunneling path from p+-GaAsSb to n-InGaAs is highlighted. To ensure complete gate control over the region where tunneling takes place, an air-bridge structure is implemented, eliminating potential leakage paths due to tunneling without gate-control. Figure 2 shows the proposed process flow. The molybdenum drain contact is deposited and patterned first, followed by mesa definition and etch. Then a HfO₂ gate dielectric and a tungsten gate are deposited after surface passivation. The air-bridge structure is formed by dry etching fins followed by a selective wet etch that undercuts the fin and suspends the air-bridges. Figure 2a shows an SEM micrograph of the air-bridge structure after lateral undercut etch. After the air-bridge formation, etching the n-InGaAs in the source region exposes the source. Then the Pd/Au contact is deposited on the p+-GaAsSb layer. The inter-layer dielectric is then deposited, via holes are opened for contact, and finally, probe pads are formed. The impacts of different structural parameters on device performance are under study.



Figure 1: Cross-sectional view of the InGaAs/GaAsSb vertical T-FET. An air-bridge structure is implemented to eliminate potential leakage paths.



Figure 2: Left: Proposed process flow for the InGaAs/GaAsSb vertical T-FET. Right: SEM micrograph of the fabricated air-bridge structure after a selective wet etch.




1. T. Yuan and T. H. Ning, Fundamentals of Modern VLSI Devices, 2^nd Edition, Cambridge: Cambridge University Press, 2004. [↩]
2. K. Gopalakrishnan, P. B. Griffin, and J. D. Plummer, “Impact ionization MOS (I-MOS)-Part I: device and circuit simulations,” IEEE Trans. Electron Devices, vol. 52, no. 1, pp. 69-76, 2005 [↩]
3. J. Appenzeller, Y.-M. Lin, J. Knoch, and P. Avouris, “Band-to-Band Tunneling in Carbon Nanotube Field-Effect Transistors,” Phys. Rev. Lett., vol. 93, p. 196805, 2004. [↩]
4. A. M. Ionescu and H. Riel, “Tunnel field-effect transistors as energy-efficient electronic switches,” Nature, vol. 479, no. 7373, pp. 329–337, 2011. [↩] [↩]

Towards Highly Scaled Gate Length Asymmetrically Strained Ge Nanowire p-MOSFETs

• Authors: W. Chern, P. Hashemi, J. T. Teherani, T. Yu, D.A. Antoniadis, J. L. Hoyt
• Sponsorship: SRC/FCRP MSD, SRC IBM Customization Grant

Ge nanowires are of interest for future sub-10-nm gate length p-MOSFETs because of the excellent electrostatic control afforded by the non-planar device geometry and the potential for high hole velocity in strained Ge.  In this work, asymmetrically strained Ge was explored and compared to biaxially strained Ge. Asymmetric strain is a strain state that is neither uniaxial nor biaxial but somewhere in between.  Asymmetric strain was generated by lateral relaxation of biaxial strain as a result of nanowire formation, due to the free surfaces that are created as shown in Figure 1. To explore asymmetric strain, biaxially strained strained Ge-on-insulator (SGOI) wafers were first fabricated using a bond and etch-back process [1]. The wafers were then used to fabricate long-channel asymmetrically strained nanowire trigate Ge p-MOSFETs and on-chip biaxially strained planar Ge p-MOSFETs (Figure 2). The enhancement in mobility for high charge density for wide asymmetrically strained nanowires is 2.0x relative to biaxially strained Ge and 15x relative to Si hole universal mobility^[1]. The enhancement in mobility promises significant improvement of the hole transport relative to both biaxially strained Ge and state-of-the-art Si, for asymmetrically strained Ge at scaled gate lengths.  Progress is being made in developing a process for highly scaled gate length transistors where the viability of asymmetrically strained Ge as a material for improving the performance of MOSFETs is under analysis.

1. W. Chern, P. Hashemi, J. T. Teherani, T. Yu, Y. Dong, G. Xia, D. A. Antoniadis, and J. L. Hoyt, “High Mobility High-κ-All-Around Asymmetrically-Strained Germanium Nanowire Trigate p-MOSFETs,” in IEDM Tech. Dig., 2012, pp. 387-390. [↩]