MTL Annual Research Report 2013

Towards Highly Scaled Gate Length Asymmetrically Strained Ge Nanowire p-MOSFETs

Ge nanowires are of interest for future sub-10-nm gate length p-MOSFETs because of the excellent electrostatic control afforded by the non-planar device geometry and the potential for high hole velocity in strained Ge.  In this work, asymmetrically strained Ge was explored and compared to biaxially strained Ge. Asymmetric strain is a strain state that is neither uniaxial nor biaxial but somewhere in between.  Asymmetric strain was generated by lateral relaxation of biaxial strain as a result of nanowire formation, due to the free surfaces that are created as shown in Figure 1. To explore asymmetric strain, biaxially strained strained Ge-on-insulator (SGOI) wafers were first fabricated using a bond and etch-back process [1]. The wafers were then used to fabricate long-channel asymmetrically strained nanowire trigate Ge p-MOSFETs and on-chip biaxially strained planar Ge p-MOSFETs (Figure 2). The enhancement in mobility for high charge density for wide asymmetrically strained nanowires is 2.0x relative to biaxially strained Ge and 15x relative to Si hole universal mobility^[1]. The enhancement in mobility promises significant improvement of the hole transport relative to both biaxially strained Ge and state-of-the-art Si, for asymmetrically strained Ge at scaled gate lengths.  Progress is being made in developing a process for highly scaled gate length transistors where the viability of asymmetrically strained Ge as a material for improving the performance of MOSFETs is under analysis.

1. W. Chern, P. Hashemi, J. T. Teherani, T. Yu, Y. Dong, G. Xia, D. A. Antoniadis, and J. L. Hoyt, “High Mobility High-κ-All-Around Asymmetrically-Strained Germanium Nanowire Trigate p-MOSFETs,” in IEDM Tech. Dig., 2012, pp. 387-390. [↩]