All entries for dimitri antoniadis

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Dimitri A. Antoniadis

• Title: Ray and Maria Stata Professor of Electrical Engineering
• Department: Department of Electrical Engineering and Computer Science

Collaborators

• T. Equi, FCRP Materials, Structures, and Devices Focus Center, Executive Director
• L. Wei, Post-Doctoral Fellow
• S. Rakheja, Post-Doctoral Fellow

Graduate Students

• J. Teherani, Res. Asst., EECS
• J. Lin, Res. Asst., EECS
• U. Radhakrishna, Res. Asst., EECS

Support Staff

• L. McCormick, Admin. Asst. II

Publications

Kim, D.-H.; del Alamo, J. A.; Antoniadis, D. A.; Li, J.; Kuo, J.-M.; Pinsukanjana, P.; Kao, Y.-C.; Chen, P.; Papavasiliou, A.; King, C.; Regan, E.; Urteaga, M.; Brar, B.; Kim, T.-W. “L_g=60 nm recessed In_0.7Ga_0.3As metal-oxide-semiconductor field-effect transistors with Al₂O₃ insulator”, Applied Phys. Lett., pp. 223507 – 223507-4, 2012.

Teherani, J.T., S. Agarwal, E. Yablonovitch, J. L. Hoyt, and D. A. Antoniadis, ” Impact of Quantization Energy and Gate Leakage in Bilayer Tunneling Transistors”, IEEE Electron Dev. Lett., Vol. 34, pp. 298-300,  2013.

Luo, J., L. Wei, C.-S. Lee, A. D. Franklin, X. Guan, E. Pop, D. A. Antoniadis, and H.-P. Wong, ” Compact Model for Carbon Nanotube Field-Effect Transistors Including Nonidealities and Calibrated With Experimental Data Down to 9-nm Gate Length,” IEEE Transaction Electr. Dev.  2013.

Xiao Gong, Genquan Han ; Fan Bai ; Shaojian Su ; Pengfei Guo ; Yue Yang ; Ran Cheng ; Dongliang Zhang ; Guangze Zhang ; Chunlai Xue ; Buwen Cheng ; Jisheng Pan ; Zheng Zhang ; Eng Soon Tok ; Antoniadis, D. ; Yee-Chia Yeo, ” Germanium–Tin (GeSn) p-Channel MOSFETs Fabricated on (100) and (111) Surface Orientations With Sub-400 ^oC Si₂H₆ Passivation”,  IEEE Electron Dev. Lett., Vol. 34, pp. 339-341,  2013.

A. Majumdar, and D. A. Antoniadis, “Possible Observation of Ballistic Contact Resistance in Wide Silicon MOSFETs “, 70^th IEEE Device Research Conference, pp. 197-198, June 2012.

U. Radhakrishna, L. Wei, D.-S. Lee, T. Palacios and D. A.  Antoniadis, “Physics-based GaN HEMT Transport and Charge Model: Experimental Verification and Performance Projection”, Proc. International Electron Devices Meeting (IEDM), pp. 319-322, 2012.

W. Chern, P. Hashemi, J. T. Teherani, T. Yu, Y. Dong, G. Xia, D. A. Antoniadis and J. L. Hoyt, “High Mobility High-κ-All-Around Asymmetrically-Strained Germanium Nanowire Trigate p-MOSFETs”, Proc. International Electron Devices Meeting (IEDM), pp. 387-390, 2012.

J. Lin, D. A. Antoniadis, and J. A. del Alamo, “Sub-30 nm InAs Quantum-Well MOSFETs with Self-aligned Metal Contacts and Sub-1 nm EOT HfO₂ Insulator”, Proc. International Electron Devices Meeting (IEDM), pp. 357-360, 2012.

A. Majumdar,  S. Bangsaruntip, G. M. Cohen, L. M. Gignac, M. Guillorn, M. M. Frank, J. W. Sleight and D. A. Antoniadis, “Room-Temperature Carrier Transport in High Performance Short-Channel Silicon Nanowire MOSFETs”, Proc. International Electron Devices Meeting (IEDM), pp. 179-182, 2012.

L. Yu, O. Mysore, L. Wei, L. Daniel, D. A. Antoniadis, I. Elfadel and D. Boning, “An Ultra-Compact Virtual Source FET Model for Deeply-Scaled Devices: Parameter Extraction and Validation for Standard Cell Libraries and Digital Circuits”, ASP-DAC 2013.

Yu, L., L. Wei, D. A. Antoniadis, E. Ibrahim, and D. Boning, “Statistical Modeling wit the Virtual Source MOSFET Model,” Proceedings of Design, Automation & Test in Europe Conferenc and Exhibition (DATE), pp. 1454-1457, 2013.

MIT Virtual Source GaNFET – High Voltage (MVSG-HV) Model: A Physics-based Compact Model for HV-GaN HEMTs

• Authors: U. Radhakrishna, T. Imada, T. Palacios, D. Antoniadis
• Sponsorship: Singapore-MIT Alliance for Research and Technology

Compact models of GaN-based high-electron-mobility transistors (HEMTs) are essential for the design of power conversion circuits such as power integrated circuits (ICs), DC-DC convertors, etc.^[1]. In this work, we propose a new physics-based transport and charge model for long-channel GaN HEMTs. The model is based on the concept of virtual source (VS) carrier transport^[2] and is extended to the drift diffusion regime. The model is fully scalable from non-velocity saturation to the velocity saturation regime. In addition, non-linear access regions are modeled as implicit-gated transistors. Self-heating effects and self-consistent charge models are included. The model is implemented in Verilog-A and is validated against state-of-the-art industry devices.

The MVSG-HV intrinsic transistor model extends a previous short-channel GaN field-effect transistor model^[3] that was based on quasi-ballistic transport to the drift-diffusion transport.  Drain-end charge modulation by pinch-off and velocity saturation is achieved smoothly as function of gate length; the resulting current has self-consistent linear- to saturation-region transition. Terminal charges are self-consistently solved by employing current continuity and Ward-Dutton charge partitioning. The access regions are modeled as implicit-gated transistors similar to the intrinsic device. Key differences are that these regions have no physical gate and an implicit-gate-overdrive is linked to the sheet resistance. Figure 1 shows the sub-circuit model along with the structure schematic. DC characteristics obtained from the model and measurements are shown in Figure 2. The model captures physics in different regions of the device and is able to replicate both static and dynamic behavior of experimental devices.



Figure 1: (a) Cross-section schematic of HV GaN HEMTs under study (b) Equivalent circuit implementation of the model that captures the intrinsic transistor and non-linear access region behavior as implicit-gated transistors.



Figure 2: Output, transfer, output conductance, and transfer conductance plots of Lg=3 μm and Lgd= 9.5 μm device. Good agreement has been achieved between the model (curves) and measurement (circles).




1. U. Mishra, L. Shen, T. E. Kazior, and Y-F Wu, “GaN-Based RF Power Devices and Amplifiers,” Proceedings of the IEEE, vol. 96, no. 2, pp. 287-305, Feb. 2008. [↩]
2. A. Khakifirooz, O. Nayfeh, and D. Antoniadis, “A Simple Semiempirical Short-Channel MOSFET Current-Voltage Model Continuous Across All Regions of Operation and Employing Only Physical Parameters,” IEEE Transactions on Electron Devices, vol. 56, pp. 1674-1680, 2009. [↩]
3. U. Radhakrishna, L. Wei, D. S. Lee, T. Palacios, and D. Antoniadis, “Physics-based GaN HEMT transport and charge model: Experimental verification and performance projection,” IEEE International Electron Devices Meeting., pp.13.6.1-13.6.4, 10-13 Dec. 2012. [↩]

Quantization in Bilayer Tunneling Transistors

• Authors: J. T. Teherani, T. Yu, D. A. Antoniadis, J. L. Hoyt
• Sponsorship: NSF E3S Center, NDSEG Fellowship

Tunneling field-effect transistors (TFETs)^[1] are promising for low-power applications due to their potential to achieve a subthreshold swing (SS) lower than 60 mV/decade at room temperature. The bilayer TFET design is a novel double-gate structure that eliminates doping in the channel of the device and creates a hole-rich and electron-rich layer using oppositely biased top and bottom gates^[2]. This gate-controlled electrostatic doping enables sharper p-n regions and a sharper density of states as there is no acceptor or donor impurity band. These benefits may allow for steeper switching of the bilayer TFET compared to conventional designs.

The structure and energy bands of a bilayer TFET are shown in Figure 1. The structure is similar to a thin-body double-gated device, except that the top and bottom gates are offset from each other. The structure is biased so as to create a hole-rich layer along the bottom gate connecting to the p+ source and an electron-rich layer along the top-gate connecting to the n+ drain. A small positive bias is applied to the drain, so that the whole structure is essentially a reverse-biased p-n junction. The small reverse-biased current is the off-state current of the device. The device can be turned on by applying a sufficient voltage across the top and bottom gates to make the electron and hole eigenstates overlap in energy. Once these states overlap, electrons can tunnel from the valence band into the conduction band. The sharpness of the transition from the off-state to the on-state depends on the sharpness of the density of states and can be degraded by parasitic tunneling through traps and other defects.

Since tunneling current is exponentially dependent on tunneling distance, on-current can be increased by decreasing the body thickness of the device. However, as the body thickness is made increasingly thin, the quantization energy of the electron and hole states becomes exceedingly large and requires a very large body voltage for the electron and hole eigenstates to overlap (Figure 2). In particular, the large body voltage is undesirable due to increased gate leakage. We have found that a 15-nm body thickness represents a reasonable tradeoff between on-state current and off-state gate leakage current in a bilayer TFET.



Figure 1: (a) Electron-hole bilayer TFET structure. (b) Structure with bias and current flow. Red arrows indicate current path. A positively biased top gate attracts electrons while a negatively biased bottom gate attracts holes. Vertical band-to-band tunneling (BTBT) takes place when sufficient voltage is applied across the device so that the electron and hole eigenstates overlap in energy. (c) Energy band diagram across cut shown in (a). A triangular well forms near the top gate for electrons and near the bottom gate for holes. (d) Potential barrier problem solved analytically.



Figure 2: Solid lines indicate the body voltage required to align the electron and hole eigenstates (required for the onset of band-to-band tunneling). A thin body thickness requires a large body voltage due to the increased confinement of electrons and holes. Dotted lines indicate the body-voltage efficiency—the change in the energy overlap of the electron and hole confined states for a change in the body voltage. The body-voltage efficiency is less than one because increasing the body voltage increases the confinement energy of electrons and holes.




1. A. C. Seabaugh and Q. Zhang, “Low-Voltage Tunnel Transistors for Beyond CMOS Logic,” in Proceedings of the IEEE, vol. 98, no. 12, pp. 2095–2110, 2010. [↩]
2. J. T. Teherani, S. Agarwal, E. Yablonovitch, J. L. Hoyt, and D. A. Antoniadis, “Impact of Quantization Energy and Gate Leakage in Bilayer Tunneling Transistors,” IEEE Electron Device Letters, vol. 34, no. 2, pp. 298 –300, Feb. 2013. [↩]

A Unified Charge-current VS Compact Model for Graphene Transistors Applicable in Analog Circuit Simulations

• Authors: S. Rakheja, H. Wang, D. Antoniadis
• Sponsorship: NSF Network for Computational Nanotechnology - NEEDS Node

With its rich physics, graphene has properties that make it a viable candidate for implementing electronic devices. For example, graphene as a two-dimensional material has a limited phase space for scattering of electrons; hence, the electrons in graphene can have a long MFP–a property that can be utilized to build high frequency devices^[1],^[2]. However, to design and simulate electronic circuits built with graphene transistors, compact device models are needed to describe electron transport in both long and short-channel graphene field effect transistors (GFETs).

In this work, we extend the compact virtual source (VS) model originally developed for silicon transistors^[3] to describe current conduction in quasi-ballistic graphene transistors. Because of the absence of bandgap in graphene, graphene can uniquely exhibit ambipolar transport^[4]. Hence, the VS model is adjusted from the original VS model for silicon to accurately describe current conduction in ambipolar regime in GFETs (see Figures 1b and 1b). The key parameters of the VS model- apparent channel mobility, µ_app, and the virtual source velocity, v_xo, are extracted from published experimental results on short-channel GFETs^[5]. It is found that v_xo in quasi-ballistic GFETs can be quite large compared to its value for silicon FETs with similar channel lengths. This velocity is attributed to the large effective mobility, µ_eff, in graphene for technologically relevant carrier concentrations (see Figure 2)^[6].

The physics of electron transport in long-channel GFETs can be described fairly accurately within the drift diffusion (DD) transport framework. The DD-model for GFETs is used to explain the experimental findings in^[7],^[8], and reasonable match with experimental data is demonstrated (see Figures 3a and 3b). Both VS and DD current models are implemented in Verilog-A to provide a platform for simulation of basic analog circuits such as frequency multipliers with graphene.

Future work includes introducing intrinsic charge partitioning, and therefore an intrinsic capacitance model, that will be strictly consistent with both the quasi-ballistic VS model in both nano-scale unipolar and ambipolar GFETs and the DD model for long-channel unipolar and ambipolar GFETs.



Figure 1a: ID versus VGS of the top gate in graphene for a VDS of 1V. Experimental data from [5] for a channel length is 240 nm and channel width of 1 µm. The extracted mobility is 1480 cm2/Vs and vxo = 2.5e7 cm/s.



Figure 1b: Output curves for the device shown in Figure 1a. Dotted lines correspond to experimental data, while solid lines correspond to the VS model.






Figure 2: Effective mobility versus carrier concentration in graphene on various substrates at room temperature. Graphene on h-BN offers the best-case effective mobility because it is lattice matched with graphene and has a weaker Fröhlich coupling of surface polar phonons with graphene sheet^[9].






Figure 3a: Experimental data (symbols) for the device of length and width = 5 µm from^[10]. The drift-diffusion model is fitted as shown in solid lines.



Figure 3b: Output characteristics for experimental data (symbols) [8] for the device of length = 1 µm and width = 2.1 µm from^[11]. The drift-diffusion model is fitted as shown in solid lines.




1. A. H. Castro Neto, F. Guinea, K. S. Novoselov, and A. K. Geim, “The electronic properties of graphene,” Review of Modern Physics, vol. 81, no. 1, pp. 109-162, Jan.-Mar. 2009. [↩]
2. H. Wang, A. Hsu, J. Wu, J. Kong, T. Palacios, “Graphene-based ambipolar RF-mixers,” IEEE Electron Device Letters, vol. 31, no. 9, pp. 906-908, 2010. [↩]
3. A. Khakifirooz, O.M. Nayfeh, and D. Antoniadis, “A simple semi-empirical semi-empirical short-channel MOSFET current-voltage model continuous across all regions of operation and employing only physical parameters,” IEEE Transactions on Electron Devices, vol. 56, no. 8, pp. 1674-1680, Aug. 2009. [↩]
4. T. Palacios, A. Hsu, and H. Wang, “Applications of graphene devices in RF communications,” IEEE Communications Magazine, vol. 48, no. 6, pp. 122-128, June 2010. [↩]
5. Y. Lin, C. Dimitrakopoulos, K.A. Jenkins, D.B. Farmer, H.-Y. Chiu, A. Grill, and P.H. Avouris, “100-GHz transistors from wafer-scale epitaxial graphene,” Science, vol. 327, no. 5966, p. 663, Feb. 2010. [↩]
6. S. Rakheja, V. Kumar, A. Naeemi, “Evaluation of the potential performance of graphene nanoribbons as on-chip interconnects (invited),” Proceedings of the IEEE, vol. 101, no.7, 2013. [↩]
7. H. Wang, A. Hsu, J. Kong, D. A. Antoniadis, and T. Palacios, “Compact virtual-source current-voltage model for top- and back-gated graphene field-effect transistors,” IEEE Transactions on Electron Devices, vol. 58, no. 5, May 2011. [↩]
8. I. Meric, M.Y. Han, A. F. Young, B. Ozyilmaz, P. Kim, and K. A. Shepard, “Current saturation in zero-bandgap graphene field-effect transistors,” Nature Nanotechnology, vol. 3, pp. 654-659, Nov. 2008. [↩]
9. S. Rakheja, V. Kumar, A. Naeemi, “Evaluation of the potential performance of graphene nanoribbons as on-chip interconnects (invited),” Proceedings of the IEEE, vol. 101, no.7, 2013. [↩]
10. H. Wang, A. Hsu, J. Kong, D. A. Antoniadis, and T. Palacios, “Compact virtual-source current-voltage model for top- and back-gated graphene field-effect transistors,” IEEE Transactions on Electron Devices, vol. 58, no. 5, May 2011. [↩]
11. Y. Lin, C. Dimitrakopoulos, K.A. Jenkins, D.B. Farmer, H.-Y. Chiu, A. Grill, and P.H. Avouris, “100-GHz transistors from wafer-scale epitaxial graphene,” Science, vol. 327, no. 5966, p. 663, Feb. 2010. [↩]