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Anantha Chandrakasan

• Title: Joseph F. & Nancy P. Keithley Professor of Electrical Engineering
• Department: Department of Electrical Engineering and Computer Science

Graduate Students

• G. Angelopoulos, Research Assistant, EECS (co-supervised with Prof. M. Medard)
• S. Bandyopadhyay, Research Assistant, EECS
• A. Biswas, Research Assistant, EECS
• K. Chen, Research Assistant, EECS (co-supervised with Prof. C. Sodini)
• N. Desai, Research Assistant, EECS
• D. El-Damak, Research Assistant, EECS
• S. Goswami, Research Assistant, EECS
• S. Ha, Research Assistant, EECS
• C. Juvekar, Research Assistant, EECS
• B. Lam, Research Assistant, EECS
• S. Lee, Research Assistant, EECS (co-supervised with Prof. H. Lee)
• P. Nadeau, Research Assistant, EECS
• A. Paidimarri, Research Assistant, EECS
• S. Park, Research Assistant, EECS (co-supervised with Prof. L. Peh)
• M. Price, Research Assistant, EECS
• P. Raina, Research Assistant, EECS
• R. Rithe, Research Assistant, EECS
• M. Siddiqui, Research Assistant, (co-supervised with Benjamin J. Vakoc)
• Y. Sinangil, Research Assistant, EECS
• Y. Song, Research Assistant, EECS (co-supervised with Prof. J. Kong)
• M. Tikekar, Research Assistant, EECS
• G. Yahalom, Research Assistant, EECS
• F. Yaul, Research Assistant, EECS
• M. Yip, Research Assistant, EECS
• D. Zhang, Research Assistant, EECS

Research Scientist

• N. Ickes

Visiting Scientists

• D. Buss (Texas Instruments)
• Y. Qui (Foxconn)

SuperUROPs

• R. Jin
• P. Suriana
• E. Taratoris
• T. Yeh
• S. Jacobs

Support Staff

• M. Flaherty, Senior Administrative Assistant

Publications

A. Paidimarri, P. M. Nadeau, P. P. Mercier, A. P. Chandrakasan , “A 2.4 GHz Multi-Channel FBAR-based Transmitter With an Integrated Pulse-Shaping Power Amplifier,” IEEE Journal of Solid-State Circuits, vol.PP, no.99, pp.1-13, April 2013.

C.-T. Huang, M. Tikekar, C. Juvekar, V. Sze, A. Chandrakasan, “A 249Mpixel/s HEVC Video-Decoder Chip for Quad Full HD Applications,” IEEE International Solid State Circuits Conference (ISSCC), pp. 162-163, Feb 2013.

R. Rithe, P. Raina, N. Ickes, S. V. Tenneti, A. P. Chandrakasan, “Reconfigurable Processor for Energy-Scalable Computational Photography,” IEEE International Solid State Circuits Conference (ISSCC), pp. 164-165, Feb 2013.

M. Qazi, A. Amerasekera, A. P. Chandrakasan, “A 3.4pJ FeRAM-Enabled D Flip-Flop in 0.13µm CMOS for Nonvolatile Processing in Digital Systems,” IEEE International Solid State Circuits Conference (ISSCC), pp. 192-193, Feb 2013.

N. Desai, J. Yoo, A. P. Chandrakasan, “A Scalable 2.9mW 1Mb/s eTextiles Body Area Network Transceiver with Remotely Powered Sensors and Bi-Directional Data Communication,” IEEE International Solid State Circuits Conference (ISSCC), pp. 206-207, Feb 2013.

M. E. Sinangil, A. P. Chandrakasan, “An SRAM Using Output Prediction to Reduce BL-Switching Activity and Statistically-Gated SA for up to 1.9× Reduction in Energy/Access ,” IEEE International Solid State Circuits Conference (ISSCC), pp. 318-319, Feb 2013.

S. Bandyopadhyay, B. Neidorff, D. Freeman, A. P. Chandrakasan, “90.6% Efficient 11MHz 22W LED Driver Using GaN FETs and Burst-Mode Controller with 0.96 Power Factor,” IEEE International Solid State Circuits Conference (ISSCC), pp. 368-369, Feb 2013.

D. El-Damak, S. Bandyopadhyay, A. Chandrakasan, “A 93% Efficiency Reconfigurable Switched-Capacitor DC-DC Converter Using On-Chip Ferroelectric Capacitors,” IEEE International Solid State Circuits Conference (ISSCC), pp. 374-375, Feb 2013.

K.-J. Lee, H. Park, J. Kong, A. P. Chandrakasan, “Demonstration of a Subthreshold FPGA using Monolithically Integrated Graphene Interconnects,” IEEE Transactions on Electron Devices, vol. 60, no. 1, pp. 383-390, Jan 2013.

P. Mercier, A. C. Lysaght, S. Bandyopadhyay, A. P. Chandrakasan, K. M. Stankovic, “Energy extraction from the biologic battery in the inner ear,” Nature Biotechnology, Nov. 2012.

Graphene-based Wide-spectrum CMOS Image Sensor

• Authors: S. Ha, A. Hsu, T. Palacios, A. P. Chandrakasan
• Sponsorship: International Iberian Nanotechnology Laboratory, Institute for Soldier Nanotechnologies

CMOS image sensors are widely used in digital multimedia applications, and its performance ramps up every year with denser integration, better noise suppression, adjustable dynamic range, and lower power^[1]. However, the band gap of silicon fundamentally limits the absorption spectrum to the visible and near-infrared light (λ < 1100nm)^[2]. In our research, we propose an integrated CMOS imager with a graphene photodetector. Thanks to its zero band gap, the graphene photodetector absorbs long wavelengths (λ > 1μm) and enables integrated circuits (ICs) for wide-spectrum imaging applications such as thermal and terahertz imaging.

In the design of the graphene photodetector, graphene’s high conductivity is a key problem because the charge generated by the photovoltaic effect at the graphene-metal junctions easily leaks back. Also, the low output impedance severely limits the output voltage of the graphene photodetector to only a few microvolts, which degrades the signal noise ratio (SNR). To resolve the leakage issue and improve SNR, we propose to use a modulated input source. The mechanical shutter working at around 1 kHz shifts the input signal out from DC region where the leakage component dominates. The modulation also suppresses flicker noise in the photodetector and the readout circuits, by a band pass filter followed by a multi-stage low noise amplifier.

Figure 1 shows the pixel circuit design of a modeled graphene photodetector and a transimpedance amplifier. Unlike p-n junction photodiodes^[3], the graphene photodetector is placed on top of the silicon substrate, requiring no extra area, so higher integration can be achieved in each pixel. The amplitude of the photocurrent is converted to voltage and then measured by an 8b-resolution ADC in a column-parallel architecture as shown in Figure 2. The pixel resolution of the prototype chip is expected to be 80 by 60.



Figure 1: Image sensor pixel design with a graphene photodetector and a differential transimpedance amplifier



Figure 2: Top view of the floor plan of a wide spectrum image sensor IC.




1. A. Fish and O. Yadid-Pecht, “Low Power CMOS Imager Circuits,” in Circuits at the Nanoscale: Communications, Imaging, and Sensing, K. Iniewski, Boca Raton: CRC Press/Taylor & Francis, 2009. [↩]
2. R. Kaufmann, “Near infrared image sensor with integrated germanium photodiodes,” Journal of Applied Physics, vol. 110, pp. 023107-6, July 2011. [↩]
3. M. Perenzoni, N. Massari, D. Stoppa, L. Pancheri, M. Malfatti, and L. Gonzo, “A 160×120-Pixels Range Camera With In-Pixel Correlated Double Sampling and Fixed-Pattern Noise Correction,” IEEE Journal of Solid-State Circuits, vol. 46, pp. 1672-1681, 2011. [↩]

A 93% Efficiency Reconfigurable Switched-Capacitor DC-DC Converter Using On-Chip Ferroelectric Capacitors

• Authors: D. El-Damak, S. Bandyopadhyay, A. P. Chandrakasan
• Sponsorship: Texas Instruments Graduate Fellowship for Women in Microelectronics

Switched-Capacitor (SC) DC-DC converters have gained significant interest as promising candidates for  integrated power conversion solution that eliminates the need for inductors. However, SC converters efficiency is limited by the conduction loss, bottom plate parasitic capacitance, and gate drive loss in addition to the overhead of the control circuits. In this work, we exploit on-chip ferroelectric capacitors (FeCaps) for charge transfer owing to their high density and extremely low bottom plate parasitic capacitance. High-efficiency conversion is achieved by combining the FeCaps with multi-gain setting converter in a reconfigurable architecture with dynamic gain selection. Figure 1 shows the top-level architecture of the system which consists of a reconfigurable switched capacitor DC-DC converter split in four interleaved modules for output voltage ripple reduction, pulse frequency modulation (PFM) logic, a clock generator,  gain selection block that includes programmable low duty cycle timers, and a voltage reference. The PFM modulation scheme is performed using a dynamic comparator whose output is fed into cascaded clock dividers, after which non-overlap clock generators to provide the multi-phase control signals. The SC converter gain setting is selected based on the ratio of the reference to the input voltage by using dynamic comparators and gain select decoder  to set the configuration of the switch matrix. The system was fabricated in 130-nm CMOS process and occupies an area of 600×610 μm² as shown in Figure 2.  The converter supports four conversion ratios (1/3-1/2-2/3-1) while supplying a wide output voltage range of 0.4V to 1.1V from 1.5V input and a load current of 20μA to 1mA. The system achieves a peak efficiency of 93% including the control overhead at load current of 500µA and output voltage of 0.96V while the SC DC-DC converter alone achieves a peak efficiency of 94%.



Figure 1: System top-level architecture



Figure 2: Chip micrograph.




Self-powered Long-range Wireless Microsensors for Industrial Applications

• Authors: N. Ickes, P. Iannucci, S. Jacobs, A. Paidimarri, X. Wang, F. Yaul, H. Balakrishnan, K. K. Gleason, A. P. Chandrakasan
• Sponsorship: Shell, Texas Instruments, NSF



Figure 1: Block diagram of the planned sensor node. Optimized, energy-efficient sensor front end and radio components will allow the entire node to be powered from ambient energy harvested from solar, vibration, or thermal sources.

Improved monitoring of industrial equipment through the use of vast networks of small, easily installed, long-lasting, reliable wireless sensor nodes has the potential to increase worker safety, decrease down time, and even minimize unnecessary preventative maintenance. While critical systems are already likely to be highly instrumented and monitored, a large, modern industrial installation (such as an oil refinery, for example) may contain thousands of pumps, fans, motors, and other ancillary equipment that is monitored only through periodic, manual inspections.  We are developing wireless microsensors to improve and automate the monitoring of this balance-of-plant equipment.

Figure 1 shows a block diagram of the planned sensor nodes.  A reconfigurable analog front end will interface to the sensors themselves.  Mechanical failures often develop slowly and can be detected early from abnormal vibrations and temperatures or minor gas leaks.  Therefore, while the front end will be adaptable to a variety of sensor types, we will primarily focus on accelerometers and thermocouples, as well as a new conductive polymer sensor for organic vapors, which is also being developed for this project.

Designing an efficient radio and network protocol is another key effort of this project. The target applications will require long- range (at least 100m) communication between the sensor nodes and the base station and high densities (up to 10,000 nodes per base station).  We are investigating ways to improve existing protocols by reducing synchronization requirements and incorporating new coding techniques (such as spinal codes), to shift more of the power consumption to the base station, where energy is less constrained.

Once deployed, the sensors must function for up to twenty years without maintenance, so each node will be entirely powered by energy scavenged from its environment.  Solar power is an attractive source for sensors deployed outdoors, but we are also investigating vibration and thermal harvesting, as these energy sources are readily available in many industrial applications and would allow sensors to be deployed in much less accessible locations.

A 90.6%, 11-MHz, 22-W LED Driver using GaN FETs and a Burst Mode Controller

• Authors: S. Bandyopadhyay, B. Neidorff, D. Freeman, A. P. Chandrakasan
• Sponsorship: MIT-MTL GaN Energy Initiative



Figure 1: Block diagram of LED driver.

With the advent of reliable, high-brightness and high-efficacy LEDs, the lighting industry is expected to see a significant growth in the near future. However, for LEDs to completely replace the traditional incandescent and CFL bulbs, the power converters within the LED drivers need more efficiency and further miniaturization. Superior figure of merit (R_ds,ONxQ_g) of gallium nitride (GaN) FETs over silicon FETs can enable both high-efficiency and  high-frequency operation, thereby making power converters smaller, more efficient, and more reliable. Using integrated controllers and drivers can reduce the number of components on the driver PCB, further miniaturizing the driver. This work focuses on demonstrating a small form factor, high-efficiency offline LED driver using GaN FETs with an integrated gate driver and controller circuit implemented on a 0.35-mm CMOS process with 3.3V/15V voltage handling capability. Figure 1 shows the architecture of the LED driver implemented. The driver achieves a peak efficiency of 90.6% and a peak power factor of 0.96. In order to operate the converter efficiently at high frequencies, a Quasi-Resonant topology is employed. The resonant circuit, formed by L_RESO and C_OUT,GaN, helps achieve Zero Voltage Switching (ZVS). An on-chip integrated burst-mode controller is implemented to control the LED current, provide power factor correction, and drive the gate of the GaN FET.

Low-power Memory Circuits

• Authors: Y. Sinangil, A. Biswas, A. P. Chandrakasan
• Sponsorship: DARPA, TSMC University Shuttle Program, STMicroelectronics

Transistor scaling has resulted in integration of more functionality on a single die. On-chip memories are responsible for a large portion of the system power, and low-voltage memory design is an important research topic^[1]. Starting at 45 nm, different process technologies are investigated to achieve low-voltage memory operation. Early silicon data predict that at a 22-nm node, 6T SRAM macros on FD-SOI can reach 6-sigma yield at VDD as low as 0.6V.

With continuous scaling, systems are getting more complex. Those complex systems usually need to meet multiple constraints and must be optimized for achieving conflicting goals. Additionally, they must perform efficiently under dynamically changing conditions. Self-aware systems can be used to achieve better system optimization by utilizing run time monitoring of critical system metrics^[2]. Figure 1-b shows measured EOP calculated by our on-chip energy sensing circuit across different temperatures and by varying total read and write operation ratios. Depending on these conditions, EOP can change by more than 2×. Thus, an energy sensing circuit that generates a digital representation of absolute energy per operation (EOP) consumed by the caches would provide useful information to the system. Moreover, memories often limit system performance. To address this trait, we use a novel body-biased sense amplifier in our SRAM (BBSA) (Figure 2). In BBSA we propose an offset compensation technique using body-biasing to reduce input-referred offset of sense-amplifiers.  BBSA can achieve a 1.9× smaller input offset voltage by using AVDDB = AVDD + 150 mV.

The block diagram of our 128-kbit SRAM with embedded energy sensing circuit is given in Figure 1-a^[3]. SRAMs are designed using an 8T bit-cell and can operate down to 0.37 V. In addition, an on-chip energy metering circuit measures run time absolute energy per operation numbers of the SRAM blocks. Active power consumed by energy sensing circuit is 0.28% of the SRAM active power. The small area and power overhead of the energy sensing circuit makes it suitable for system-level power management.



Figure 1: (a) Chip block diagram. (b) Measured EOP under different read operation to write operation ratios and temperatures. EOP changes by more than 2× across different conditions.



Figure 2: Body-biased sense amplifier circuit diagram. BBSA utilizes body biasing to reduce input-referred offset voltage of its input transistors (M1 and M2) by controlling their body voltages (VP1 and VP2). M3 to M6 PMOS transistors drive VP1 and VP2 to either AVDD or AVDDB depending on the outcome of the calibration process.




1. N. Ickes, Y. Sinangil, F. Pappalardo, E. Guidetti, and A. P. Chandrakasan, “A 10 pJ/cycle ultra-low-voltage 32-bit microprocessor system-on–chip,” ESSCIRC, pp. 159-162, Sep. 2011. [↩]
2. H. Hoffmann, J. Holt, G. Kurian, E. Lau, M. Maggio, J. E. Miller, S. M. Neuman, M. Sinangil, Y. Sinangil, A. Agarwal, A. P. Chandrakasan, and S. Devadas, “Self-aware Computing in the Angstrom Processor,” Proceedings of the 49th Design Automation Conference (DAC), June 2012. [↩]
3. Y. Sinangil and A. P. Chandrakasan, “An Embedded Energy Monitoring Circuit for a 128kbit SRAM with Body-biased Sense-Amplifiers,” A-SSCC, Nov. 2012. [↩]

4K Ultra HD Video Decoder for H.265/HEVC

• Authors: M. Tikekar, C.-T. Huang, C. Juvekar, A. P. Chandrakasan
• Sponsorship: Texas Instruments



Figure 1: Split system pipeline for HEVC decoder to save 24KB of Coeff SRAM and address variable DRAM latency.

High Efficiency Video Coding (HEVC)^[1], the latest video standard, uses larger and variable-sized coding units and longer interpolation filters than H.264/AVC to better exploit redundancy in video signals. These algorithmic techniques enable a 50% decrease in bitrate at the cost of increased computational complexity; external memory bandwidth; and, for ASIC implementations, on-chip SRAM of the video codec. To handle all coding unit sizes from 8×8 to 64×64, we develop a variable-sized system pipeline^[2]. The pipeline is split into two groups – one with entropy decoding and the other with all the pixel processing, as shown in Figure 1. First-in, first-out (FIFO)-based buffering between the two groups allows the chip to work with variable DRAM latency. Further, the FIFO is sized for transform units, which are smaller than coding units, to save 24 KB of SRAM. Similarly, the prediction engine is designed to process pixels in 32×32 blocks to save another 36 KB of SRAM. HEVC inverse transform has 8x logic and 16x memory complexity compared to H.264/AVC owing to 32×32 transforms and higher bit-precision multiplications. This work uses mathematical properties of the inverse transform to enable an area-efficient implementation using multiple constant multiplications^[3]. The prediction and inverse transform engines are designed for all 25 prediction unit types including symmetric and asymmetric partitions and all 8 transform units of square and non-square sizes. A high-throughput cache and a DRAM-latency aware memory map are designed to reduce the large DRAM bandwidth requirement by 67% and save 122mW of DRAM access power. The chip is built for the HEVC Working Draft 4 Low Complexity configuration and occupies 1.77mm² in 40nm CMOS. It performs 4K Ultra HD 30fps video decoding at 200MHz while consuming 1.19nJ/pixel of normalized system power.

1. G. Sullivan, J. Ohm-Raimer, W.-J. Han and T. Wiegand, IEEE Transactions on Circuits and Systems for Video Technology, vol. 22, no. 12, pp. 1649-1668, 2012. [↩]
2. C.-T. Huang, M. Tikekar, C. Juvekar, V. Sze, A. Chandrakasan, “A 249MPixel/s HEVC video-decoder chip for Quad Full HD applications,” Digest of Technical Papers IEEE International Solid-State Circuits Conference (ISSCC), pp. 162-163, Feb. 2013. [↩]
3. M. Potkonjak, M. B. Srivastava, A. P. Chandrakasan, “Multiple constant multiplications: efficient and versatile framework and algorithms for exploring common subexpression elimination,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 15, no. 2, pp. 151-156, Feb. 1996. [↩]