All entries for III-V materials

• Print This Page
• Download as PDF

A Ballistic Transport Model for III-V HEMTs and MOSFETs

• Authors: S. Warnock, J. A. del Alamo
• Sponsorship: SRC/FCRP MSD

As silicon metal-oxide-semiconductor field-effect transistors (MOSFETs) keep scaling down in size, fundamental physical limits threaten the continued improvement on their logic performance. With silicon approaching these limits, MOSFETs designed with III-V semiconductors have emerged as promising candidates to replace them. The low-effective mass of various III-V materials such as InGaAs and InAs allow both faster and more power efficient performance^[1]. However, one of the key challenges, particularly as devices continue to shrink, is to understand the importance of non-idealities in field-effect transistor (FET) structures. High-electron-mobility transistors (HEMTs) are III-V quantum-well FETs that can be used to explore many issues of relevance to future III-V MOSFETs. HEMTs are worthwhile transistors in their own right, but they are also simpler than III-V MOSFETs and therefore allow a more thorough exploration into the basic transport physics of a quantum-well III-V device.

HEMT experimental data show that electrons travel ballistically at gate lengths of 30-40 nm, suggesting that a ballistic transport model will become only more accurate as channel lengths are scaled down to 10 nm. We investigate to what extent this is true in III-V MOSFETs and also study the impact of short channel effects and other parasitics inherent in a III-V design.

To accomplish these goals, we have developed a flexible transistor model in MATLAB based on a ballistic theory of transport. The model uses, at its core, a one-dimensional, self-consistent Poisson-Schrödinger simulation of the heterostructure of the transistor. We then add extrinsic device parameters such as source and drain parasitic resistances (R_S and R_D), as well as appropriate values for the drain-induced barrier lowering (DIBL) and a distribution of interface trap states across the band gap at the semiconductor-oxide interface (D_it). We first used HEMTs to calibrate the model’s validity with regards to the current-voltage characteristics. Due to the absence of a gate oxide, HEMTs do not suffer from interface states. We then turned to the physics of relevance to III-V MOSFETs, particularly the effects of D_it on the C-V and I-V characteristics. We can use our model to extract trap density as a function of energy in the bandgap of the barrier semiconductor.  Figure 1 shows the C-V curves for a simulated MOSFET structure first with no D_it, and then fitted to an experimental C-V curve using the D_it distribution shown in Figure 2. The MOSFET used for this comparison is an Al₂O₃ buried-channel device fabricated by Lin et al. and described in^[2]. Ultimately, the ability to correctly model and predict device behavior will help identify the problems that need attention in the iterations of future device fabrication.



Figure 1: C-V characteristics of model simulation against experimental data for the long-channel Al2O3 III-V MOSFET in [2], at room temperature. The threshold voltage was fit with I-V sub-threshold characteristics.



Figure 2. Dit distribution for III-V MOSFET in [2], extracted from C-V characteristics in Figure 1. The Dit distribution is inside the band gap of the InP barrier layer.




1. J. A. del Alamo, “Nanometer-scale electronics with III-V compound semiconductors,” Nature, vol. 479, pp. 317-323, Nov. 2011. [↩]
2. J. Lin, D. A. Antoniadis, and J. A. del Alamo, “Sub-30 nm InAs Quantum-Well MOSFETs with Self-aligned Metal Contacts and Sub-1 nm EOT HfO2 Insulator,” IEEE International Electron Devices Meeting, San Francisco, CA, Dec. 10-12, 2012, pp. 757-760. [↩]

Nano-scale Metal Contacts for III-V FETs

• Authors: W. Lu, J. A. del Alamo
• Sponsorship: SRC/FCRP MSD, Intel

In the last few years, III-V compound semiconductors have emerged as a promising family of materials to replace silicon in logic applications^[1]. Novel III-V MOSFET prototypes with superior electron-transport properties have been recently demonstrated^[2]. One of the challenges to obtain high performance is to achieve a very low ohmic contact resistance. As transistor scaling continues, it is important to fabricate and characterize high-quality ohmic contacts with nanometer-scale contact length. In this project, a nano-scale transmission line model (nano-TLM) structure is being developed to study and optimize metal contacts for III-V field-effect transistors.

This works builds on prior research in our group on the fabrication and characterization of nanoscale contacts to III-V FET structures^[3]. Our nano-TLM structure comprises a Mo contact on an InGaAs heterostructure, with various contact lengths (L_c) and spacings (L_d). The Mo contact is patterned by electron beam lithography, followed by reactive-ion etching (RIE). The mesa isolation and contact pads are fabricated by a series of lithography, RIE, and lift-off processes. The ohmic contact is annealed at 400 °C for 40 s. Figure 1 shows a nano-TLM with L_c = 19 nm, the smallest contacts we have fabricated at present. The finished test structures are characterized using Kelvin 4-terminal measurement.  We developed a 2-D circuit model to extract the contact resistivity, semiconductor sheet resistance, and metal sheet resistance. Figure 2 shows resistance measurements on Mo-n⁺-InGaAs structures with 80-nm contact length and various contact spacings. From measurements of this kind in several structures, an average contact resistivity of 0.6 Ω∙μm² is obtained.

Our research will continue to optimize the contact fabrication to achieve lower contact resistance and further scaling. We will also investigate the contact resistance to a buried channel. We will further explore metals contacts on p-type Sb-based heterostructures, which are as critical as the n-type counterpart but in great need of a high-quality ohmic contact.



Figure 1: SEM image showing the top view of a Mo-n+-InGaAs nano-TLM structure, with contact length Lc = 19 nm. The inset is a close view of Mo contacts at the edge of the mesa.



Figure 2: Experimental nano-TLM resistance of test structures with average contact length of 80 nm. The values of ρc, Rsh, and Rshm are extracted by the 2D nano-TLM model. The insets show the two configurations in the Kelvin measurements.




1. J. A. del Alamo, “Nanometre-scale electronics with III-V compound semiconductors,” Nature, vol. 479, no. 7373, pp. 317-323, Nov. 2011. [↩]
2. J. Lin, D. A. Antoniadis, and J. A. del Alamo, “Sub-30 nm InAs quantum-well MOSFETs with self-aligned metal contacts and sub-1 nm EOT HfO2 insulator.” IEEE International Electron Devices Meeting, San Francisco, CA, December 10-12, 2012, pp. 757-760. [↩]
3. A. Guo and J. A. del Alamo, “Mo/n⁺-InGaAs nanocontacts for future III-V MOSFETs,” 25^th International Conference on Indium Phosphide and Related Materials, Kobe, Japan, May 19-23, 2013. [↩]