All entries for duane boning

• Print This Page
• Download as PDF

Die-level CMP Model Combining Pattern Density and Feature Size Effects

• Authors: W. Fan, D. S. Boning
• Sponsorship: SRC/SEMATECH Engineering Research Center for Environmentally Benign Semiconductor Manufacturing

In our previous work on CMP modeling, we developed an original physical die-level model to understand the pattern density dependence of planarization since it is known to be the dominant effect of die-level non-uniformity ^[1] . However, a significant variation with layout feature size is also observed in oxide CMP ^[2] . A recent modeling improvement focuses on feature size effects based on empirical die-level models ^[3] . A physically-based die-level model including both pattern density and feature size effects is desired.

To understand the feature size effect, an extended physical die-level model is developed by considering the interactions between CMP pad asperities and step features on a chip. The extended die-level model attributes feature size dependence on pad asperity size and asperity shape. As shown in Figure 1, although both features have same pattern density, small feature planarization is faster than in large features because no down area removal occurs until a late polishing stage. Since the shape of a step feature during CMP is not ideal due to the structure corner roll off, a parabolic shape approximation can be made to utilize the Greenwood-Williamson approach including the curvature of up and down areas of each feature ^[3] . Then Hertzian contact theory ^[4] is applied to calculate pressure distribution, and Preston’s law ^[5] is used to estimate the die-level topography evolution during the CMP process. A full-chip simulation on an MIT standard STI CMP test layout shows that small features are planarized faster than large features (Figure 2), even though they have same pattern density.



Figure 1: Contact between asperities and step features with 50% density on a chip: (a) large feature size. The asperities can touch both up area and down areas (b) small feature size. The asperities can only touch up area in the early stage of polishing.



Figure 2: Feature (Pitch) size effect in CMP. Step height evolution simulated by the extended die-particle-level model for 50% density region of MIT standard test layout. Small features (10 µm pitch) are planarized very fast because only up area material removal happens.




1. X. Xie, “Physical understanding and modeling of chemical mechanical planarization in dielectric materials,” Ph.D. thesis, Massachusetts Institute of Technology, Cambridge, 2007. [↩]
2. R. Rzehak, “Pitch-dependence in oxide CMP,” in Proc. Eleventh International Conference on Chemical-Mechanical Polish Planarization for ULSI Multilevel Interconnection (CMP-MIC), 2006, p. 137. [↩]
3. B. Vasilev, R. Rzehak, S. Bott, P. Kucher, and J. W. Bartha, “Greenwood-Williamson model combining pattern-density and pattern-size effects in CMP,” IEEE Transactions On Semiconductor Manufacturing, vol. 24, no. 2, pp. 338-347, May 2011. [↩] [↩]
4. K. L. Johnson, Contact Mechanics. Cambridge: Cambridge University Press, 1985. [↩]
5. F. Preston, “The theory and design of plate glass polishing machines,” Journal of the Society of Glass Technology, vol. 11, pp. 214-256, 1927. [↩]

CMP Slurry Abrasive Particle Agglomeration Modeling

• Authors: J. M. Johnson, D. S. Boning
• Sponsorship: SRC/SEMATECH Engineering Research Center for Environmentally Benign Semiconductor Manufacturing, Intel

Previously we proposed a particle agglomeration model for chemical mechanical planarization (CMP) with the primary motivation of understanding the creation and behavior of the agglomerated slurry abrasive particles during the CMP process.  The particles are known to be a major cause of defectivity, poor consumable utility, and process variation. In this year’s work, we extend the model to include the effect of shear forces during CMP and to utilize a more sophisticated model of the double layer interactions between slurry abrasive particles in order to account for the charge effects of chemical additives. We also conducted fundamental experiments to observe agglomeration in non-commercial, experimentally created simple slurry mixtures (see Figure 1).

Our model considers the CMP slurry composition as a colloidal suspension of charged colloidal particles in an electrically neutral aqueous electrolyte. First, a theoretical relationship between the measurable chemical parameters of the slurry’s electrolyte (pH, conductivity/ionic strength), the surface potential of the abrasive particles, and subsequent zeta potential is established. Secondly, this potential is employed in a modified DVLO interaction potential model to determine the pair-wise particle interaction potentials due to both the attractive van Der Waals forces and repulsive electrostatic interactions as a function of the chemical parameters. Then, the total interaction potential created is used to define a stability ratio, which is combined with the shear rate of the process to calculate the orthokinetic aggregation rate constant. Finally, these rate constants are used in a discrete population balance framework to describe the growth of the slurry abrasive particle size distribution with respect to time and composition in a matter analogous to physical particle size distribution measurements.

We focus on the fundamental chemical and mechanical mechanisms by which slurry abrasive particles intended for planarization form agglomerates. We predict the formation of these agglomerates using measureable parameters and metrics of the slurry. The theoretical model described is empirically validated using literature and our own fundamental experimental data (shown in Figure 2).

Our model provides both a qualitative and quantitative description of agglomeration of slurry abrasive particles during CMP that will enable more accurate process control, increased consumable utility, and possible reduction of defectivity. Current work is focused on experimental development, validation, and extension of the theoretical model.



Figure 1: SEM of experimentally-created slurry at basic pH.



Figure 2: Model vs. experimental data for experimental slurry.




A Low-power SAR ADC with Redundancy

• Authors: A. H. Chang, H.-S. Lee, D. S. Boning
• Sponsorship: Masdar Institute of Science and Technology

Technology scaling has enabled low-power operations in digital integrated circuits.  Therefore, the trend to move analog-to-digital operations upstream to allow more signal-processing to shift from the analog domain to the digital domain is inevitable. As most real world signals remain analog, the design of high-performance and low-power analog-digital converters (ADC) plays a key role in the success of future integrated system design. In this research, we focus on designing a (1) robust, (2) low-power, and (3) high-performance time-interleaved successive-approximation-register (SAR) ADCs. The SAR architecture is adopted because of its good digital compatibility and high energy efficiency while achieving high sampling rates.

The robustness of SAR ADCs is achieved by analyzing the effectiveness of redundancy (digital error correction) ^{[1] [2]} in improving sampling rates and its immunity from incomplete bit-settling errors. Analysis shows that the redundancy algorithm does not help improve sampling rate in all SAR ADC designs; instead, the maximum sampling rate depends on the settling time constant (τ) and the relative magnitude of the ADC delay components ^[3] . As shown in Figure 1, in order to benefit from redundancy algorithm, τ has to be more than 50ps.

The low-power operation is achieved by combining the merged capacitor switching algorithm ^[4] and split capacitive array ^[5] . The merged capacitor-switching algorithm suffers from its sensitivity to the parasitic capacitance on the outputs of the capacitive DAC. The split capacitive array suffers from 4x loss in signal power to keep voltage below the supply rail on the sub-DAC and from the mismatch problem between the fractional bridge capacitor to other capacitors in the DAC. Both issues are researched and resolved in our design. A new digital calibration scheme is developed to digitally calibrate the ADCs to resolve the mismatches and parasitic issues. Our design also incorporates an asynchronous on-chip pulse generator to avoid synchronous high-power clock distribution circuit on-chip. The overall SAR ADCs architecture is depicted in Figure 2.



Figure 1: Speed improvement from adopting redundancy ^[3]



Figure 2: Overall SAR ADCs architectures.




1. F. Futtner, “A 1.2V 10b 20MSample/s non-binary successive approximation ADC in 0.13μm CMOS,” in IEEE International Solid-State Circuit Conference Digest of Technical Papers, 2002, pp. 136-137. [↩]
2. T. Ogawa, H. Kobayashi, M. Hotta, Y. Takahashi, H. San, and N. Takai, “SAR ADC Algorithm with redundancy,” in IEEE APCCAS, pp. 268-271, Nov. 2008. [↩]
3. A. H. Chang, H.-S. Lee, and D. S. Boning, “Redundancy in SAR ADCs,” in Great Lakes Symposium on VLSI, May 2011. [↩] [↩]
4. V. Hariprasath, J. Guerber, S.-H. Lee, and U.-K. Moon, “Merged capacitor switching based SAR ADC with highest switching energy-efficiency,” Electronics Letters, vol. 46, pp. 620-621, Apr. 2010. [↩]
5. Y. Chen, X. Zhu, H. Tamura, M. Kibune, Y. Tomita, T. Hamada, M. Yoshioka, K. Ishikawa, T. Takayama, J. Ogawa, S. Tsukamoto, and T. Kuroda, “Split capacitor DAC mismatch calibration in successive approximation ADC,” in IEEE Custom Integrated Circuits Conference, 2009, pp. 279 –282. [↩]

An On-Chip Test Circuit for Characterization of MEMS Resonator

• Authors: J. H. Lee, D. Weinstein, D. S. Boning
• Sponsorship: SRC/FCRP IFC

Electromechanical resonators such as quartz crystals, surface acoustic wave (SAW) resonators, and ceramic resonators have become essential components in electronic systems. However, due to their large footprint and difficulty in integrating with CMOS processes, there has been much development in realizing microelectromechanical system (MEMS) resonators that achieve comparable performance yet have smaller footprint and are compatible with CMOS. As with other semiconductor devices, with increasing frequency and with decreasing device size into the submicron scale, variability has started to become a critical issue in MEMS resonators. However, one of the critical challenges is the lack of a characterization method that is accurate but efficient enough to be used for testing the large number of devices necessary to acquire accurate statistical distribution of the parameters of interest. This project proposes an on-chip test circuit that can accurately characterize a large number of resonators for variation analysis and that is general enough that it can be used with a wide range of resonators, not limited to specific frequencies or other properties. The proposed test circuit is based on a transient step response method using a voltage step that can accurately measure the resonant frequencies and the quality factor of devices ^[1] . The circuit employs a sub-sampling method to capture the high-frequency decay signal ^[2] and a simple analog-to-digital converter (ADC) ^[3] allowing complete digital interface, an important feature for test automation. SPICE level simulation combined with a behavioral simulation tool that was developed showed acceptable extraction errors of <1% for RS, <0.1% for Lx, <0.1% for Cx, <100 ppm for fs, and <1% for Qs. A test chip implementing the proposed test circuit has been designed and fabricated in NSC 0.18-um CMOS process.



Table 1: Detailed specification of the test chip.



Figure 1: Die photo of the fabricated test chip.




1. M. Zhang, N. Llaser, H. Mathias, and F. Rodes, “CMOS offset-free circuit for resonator quality factor measurement,” IEEE Electronic Letters, vol. 46, no. 10, p. 706, May 2010. [↩]
2. R. Ho, B. Amrutur, K. Mai, B. Wilburn, T. Mori, and M. Horowitz, “Applications of on-chip samplers for test and measurement of integrated circuits,” in Proc. 1998 IEEE Symposium on VLSI Circuits, June, 1998, pp. 138-139. [↩]
3. E. Alon, V. Stojanović, and M. A. Horowitz, “Circuits and techniques for high-resolution measurement of on-chip power supply noise,” IEEE Journal of Solid-State Circuits, vol. 40, no. 4, pp. 820-828, Apr. 2005. [↩]

Validation of an Ultra-compact Virtual Source FET Model for Deeply Scaled Standard Cell Libraries and Digital Circuits

• Authors: L. Yu, D. S. Boning
• Sponsorship: MIT/Masdar Institute Program

In this work, the virtual source (VS) charge-based compact model is validated for standard cell libraries and digital circuits. The VS model is a simple analytical ultra-compact model for deeply scaled CMOS transistors with guaranteed continuity in current, charges, and their derivatives in all operation regions ^{[1] [2]} . With only a modest number of physically meaningful parameters, the extended VS compact model includes all of the main physical effects in nanometer technologies. The VS model is verified with simulated data from a well-characterized, industrial 40-nm bulk silicon model. Standard cell library characterization is also conducted using both the VS FET model and its “golden” industrial counterpart with excellent agreement between the timing results of the two models. Finally, a 1001-stage inverter chain and a 32-bit ripple-adder are employed as test cases in a vendor CAD environment to validate the use of the VS model for large-scale digital circuit applications. Parametric V_dd sweeps show that the VS model is ready for usage in low-power design methodologies.

The first circuit we consider is an inverter undergoing trapezoidal input transitions. This basic example is used to illustrate several important features of our calibrated VS model. It is well known that the charging and discharging activities during input gate transitions require precise balancing of both static and dynamic behavior of the NFET and PFET transistors. The output voltage waveforms using the VS model in comparison with the industry-standard BSIM4 model are depicted in Figure 1. The input slew is fixed at 10ps and the load (fanout) are 1, 2, and 4. The average delay error between the VS model and the “golden” or baseline BSIM4 model is 0.88%, and the 10% -90% rising/falling time errors are 0.92%/1.11%. This timing error is a good indication of the accuracy of the transient calibration of the proposed VS model.

To further verify the calibrated VS model, a 32-bit ripple-carry adder is designed in the targeted technology (40-nm bulk CMOS), and the transient waveform of the critical path is compared using VS and BSIM4 models. The simulation environment and the SPICE convergence setting using both models are exactly the same. The test circuit includes 0.9k transistors in total belonging to various library cell types (INV, NAND, NOR and XOR). We select the worst-case delay for a 32-bit add operation. To show the robustness of the VS model for low-power design, the supply voltage V_dd is swept from 0.6V to 0.9V. The transient signals C_in0 and C_out32 at different V_dd from both VS and BSIM4 model are shown in Figure 2, which demonstrates that the output signals of the two models have excellent matching. The average delay mismatch under all V_dd conditions is about 0.3%.  The simulation we conduct achieves an average runtime speed up of 7.6X, which is in line with the order of magnitude reduction in the number of VS parameters.



Figure 1: Transient response waveform for an inverter chain with various input fanouts.



Figure 2: Critical path transient waveform for a 32-bit ripple-adder with Vdd from 0.65V to 0.9V.




1. A. Khakifirooz et al. “A simple semi-empirical short-channel MOSFET current-voltage model continuous across all regions of operation and employing only physical parameters,” IEEE Trans. on Electron Devices, pp. 1674-1680, Aug. 2009. [↩]
2. L. Wei et al. “Virtual-source-based self-consistent current and charge FET models: From ballistic to drift-diffusion velocity-saturation operation,” IEEE Trans. on Electron Devices, pp. 1-9, 2012. [↩]

Duane S. Boning

• Title: Professor
• Department: Department of Electrical Engineering and Computer Science

Collaborators

• A. Elfadel, Masdar Institute
• A. Philipossian, Univ. of Arizona
• H. Taylor, NTU, Singapore

Graduate Students

• K. Balakrishnan, Res. Asst., EECS
• A. Chang, Res. Asst., EECS
• W. Fan, Res. Asst., EECS
• C. GoGwilt, Res. Asst., EECS
• J. Lee, Res. Asst., EECS
• J. Johnson, Res. Asst., EECS
• L. Yu, Res. Asst., EECS

Support Staff

• G. Lindsay, Admin. Asst. II
• M. Whiting, Admin. Asst. II

Publications

N. Drego,  A. Chandrakasan, D. Boning, and D. Shah, “Reduction of Variation-Induced Energy Overhead in Multi-core Processors,” IEEE Transactions on Computer-Aided Design, vol. 30, no. 6, pp. 891-904, June 2011.

H. Taylor, K. Smistrup, and D. Boning, “Modeling and simulation of stamp deflections in nanoimprint lithography: exploiting backside grooves to enhance residual layer thickness uniformity,” Microelectronic Engineering, vol. 88, no. 8, pp. 2154-2157, August 2011.

H. Taylor, D. Boning, and C. Iliescu, “A razor-blade test of the demolding energy in a thermoplastic embossing process,” Journal of Micromechanics and Microengineering, vol. 21, no. 6, p. 067002, June  2011.

R. K. Jena, H. K. Taylor, Y. C. Lam, D. S. Boning, and C. Y. Yue, “Effect of polymer orientation on pattern replication in a micro-hot embossing process: experiments and numerical simulation,” Journal of Micromechanics and Microengineering, vol. 21, no. 6, p. 065007, June  2011.

A. H. Chang, D. Boning, and H.-S. Lee, “Redundancy in SAR ADCs,” Great Lakes Symposium on Very Large Scale Integration (GLSVLSI), Lausanne, Switzerland, May 2011.

K. Balakrishnan, K. A. Jenkins, and D. Boning, “A Ring Oscillator-Based Test Structure for AC Variability Characterization of Individual MOSFETs,” 2^nd European Workshop on CMOS Variability (VARI), 4 pages, Grenoble, France, May 2011.

W. Y. Zhang, X. Li, R. Rutenbar, K. Balakrishnan, and D. Boning, “Toward Efficient Spatial Variation Decomposition via Sparse Regression,” IEEE International Conference on Computer-Aided Design (ICCAD), Nov. 2011.

W. Fan, D. Boning, Y. Zhuang, Y. Sampurno, A. Philipossian, M. Moinpour and D. Hooper, “Characterization of CMP Pad Surface Properties and Aging Effects,” International Conference on Planarization Technology (ICPT), Seoul, Korea, Nov. 2011.

J. Johnson, D. Boning, G.-S. Kim, R. Mudhivarthi, P. Safier, and K. Pate, “Slurry Particle Agglomeration Model for Chemical Mechanical Planarization (CMP),” International Conference on Planarization Technology (ICPT), Seoul, Korea, Nov. 2011.

A. H. Chang, K. Zuo, J. Wang, D. Yu, and D. Boning, “Test Structure, Circuits and Extraction Methods to Determine the Radius of Influence of STI and Polysilicon Pattern Density,” IEEE International Symposium on Quality Electronic Design (ISQED), March 2012.

L. Yu, W.-Y. Chang, K. Zuo, J. Wang, D. Yu, and D. Boning, “Methodology for Analysis of TSV Stress Induced Transistor Variation and Circuit Performance,” IEEE International Symposium on Quality Electronic Design (ISQED), March 2012.

W. Zhang, K. Balakrishnan, X. Li, D. Boning, E. Acar, F. Liu, and R. A. Rutenbar, “Spatial Variation Decomposition via Sparse Regression,” International Conference on IC Design and Technology (ICICDT), Austin, TX, May 2012.