All entries for david perreault

David Perreault

Title: Professor
Department: Department of Electrical Engineering and Computer Science

Collaborators

K. Afridi, MIT
J. Kassakian, MIT
J. Lang, MIT
S. Leeb, MIT
J. Kirtley, MIT
J. Dawson, MIT
T. Palacios, MIT
J. del Alamo, MIT
T. Barton, MIT
C. Sullivan, Dartmouth
M. Allen, Georgia Tech.

Graduate Students

David Giuliano (EECS)
Wei Li (EECS)
Minjie Chen (EECS)
Seungbum Lim (EECS)
Samantha Gunter (EECS)
Wardah Inam (EECS)
Alexander Jurkov (EECS)
Juan Santiago (EECS)

Support Staff

Donna Gale, Administrative Assistant

Publications

Pierquet, B.J. and D.J. Perreault, “A Single-Phase Photovoltaic Inverter Topology with a Series-Connected Power Buffer,” IEEE Transactions on Power Electronics, Vol. 28, No. 10, pp. 4603-4611, Oct. 2013.

Araghchini, M., J. Chen, V. Doan-Nguyen, D.V. Harburg, D. Jin, J. Kim, M.-S. Kim, S. Lim, B. Lu, D. Piedra, J. Qiu, J. Ranson, J.A. del Alamo, G. DesGroseilliers, F. Herrault, J.H. Lang, C.G. Levey, C. Murray, D.M. Otten, T. Palacios, D.J. Perreault, and C.R. Sullivan, “A Technology Overview of the PowerChip Development Program,” IEEE Transactions on Power Electronics, Vol. 28, No. 9, pp. 4182-4201, Sep. 2013.

Sagneri, A.D., D.I. Anderson, and D.J. Perreault, “Optimization of Transistors for Very High Frequency dc-dc Converters,” IEEE Transactions on Power Electronics, Vol. 28, No. 7, pp. 3614-3626, July 2013.

Pilawa-Podgurski, R.C.N. and D.J. Perreault, “Sub-Module Integrated Distributed Maximum Power Point Tracking for Solar Photovoltaic Applications,” IEEE Transactions on Power Electronics, Vol. 28, No. 6, pp. 2957-2967, June 2013.

Burkhart, J., R. Korsunsky and D.J. Perreault, “Design Methodology for a Very High Frequency Resonant Boost Converter,” IEEE Transactions on Power Electronics, Vol. 28, No. 4, pp. 1929-1937, April 2013.

Barton, T.W., J.L. Dawson and D.J. Perreault, “Experimental Validation of a Four-Way Outphasing Combiner for Microwave Power Amplification,” IEEE Microwave and Wireless Component Letters, Vol. 23, No. 1, pp. 28-30, Jan. 2013.

Qiu, Y., D.J. Perreault, T.A. Keim, and J.G. Kassakian, “Nonlinear System Modeling, Optimal Cam Design, and Advanced System Control for an Electromechanical Engine Valve Drive,” IEEE/ASME Transactions on Mechatronics, Vol. 17, No. 6, pp. 1098-1110, Dec. 2012.

Godoy, P.A., S. Chung, T.W. Barton, D.J. Perreault, and J.L. Dawson “A 2.4-GHz, 27-dBm Asymmetric Multilevel Outphasing Power Amplifier in 65-nm CMOS”, IEEE Journal of Solid-State Circuits, Vol. 47, No. 10, pp. 2372-2384, October 2012.

Han, Y. and D.J. Perreault, “Inductor Design Methods with Low-Permeability RF Core Materials,” IEEE Transactions on Industry Applications, Vol. 48, No. 5, pp. 1616-1627, Sep/Oct 2012.

Pilawa-Podgurski, R.C.N. and D.J. Perreault, “Merged Two-Stage Power Converter with Soft-Charging Switched-Capacitor Stage in 180 nm CMOS,” IEEE Journal of Solid-State Circuits, Vol. 47, No. 7, pp. 1557-1567, July 2012.

Han, Y., A. Li, G. Cheung, C.R. Sullivan, and D.J. Perreault, “Evaluation of Magnetic Materials for Very High Frequency Power Applications,” IEEE Transactions on Power Electronics, Vol. 27, No. 1, pp. 425-435, Jan. 2012.

Hu, J., A.D. Sagneri, J.M. Rivas, Y. Han, S.M. Davis, and D.J. Perreault, “High-Frequency Resonant SEPIC Converter with Wide Input and Output Voltage Ranges,” IEEE Transactions on Power Electronics, Vol. 27, No. 1, pp. 189-200, Jan. 2012.

Rivas, J.M., O. Leitermann, Y. Han, and D.J. Perreault, “A Very High Frequency dc-dc Converter Based on a Class Phi-2 Resonant Inverter,” IEEE Transactions on Power Electronics, Vol. 26, No. 10, pp. 2980-2992, Oct. 2011.

D.J. Perreault, “A New Power Combining and Outphasing Modulation System for High-Efficiency Power Amplification,” IEEE Transactions on Circuits and Systems – I, Vol. 58, No. 8, pp. 1713-1726, Aug. 2011.

Methodology for the Optimal Design of PEV Charging Systems with Multiple Chargers and Distributed Resources

Authors: S. J. Gunter, D. J. Perreault, K. K. Afridi
Sponsorship: Siemens Corporate Research

Figure 1: A PEV public charging system configuration with two distribution voltage levels. This configuration has two charging locations and three possible locations for the renewable DG and storage units.

Increased penetration of plug-in electric vehicles (PEVs) will necessitate deployment of a large number of PEV chargers^[1],^[2], but chargers can incur substantial operating costs and strain the distribution grid^[3],^[4]. Pairing these PEV chargers with renewable distributed generation (DG) and energy storage can alleviate negative impacts on the distribution grid and help meet renewable portfolio goals. The optimal design of such integrated charging systems depends on a number of factors, including their geographic location and the expected charging profiles. To address this design challenge, we developed an optimization methodology with respect to system lifecycle cost for designing integrated PEV charging systems with multiple PEV chargers and distributed resources.

This methodology is used to study optimal system designs for public charging at a retail business and on a university campus. In both cases, we consider a configuration with one grid connection point, two charging locations, and three possible locations for renewable DG and storage as shown in Figure 1. In cases where the addition of PEV charging can cause a demand charge to be incurred, it is shown that if charging is coincident in time with DG power production, then the optimal design is one that uses solar DG and the minimum amount of lead-acid storage needed to limit the amount of power drawn from the grid to less than the level that triggers a demand charge. However, if charging is not completely coincident with DG power production, the optimal design decision is more complicated and depends on the level of existing load. When non-negligible distribution system losses occur between charger locations, such as due to transformers and long cables, it is shown that the size and location of the DG and storage unit depend on, among other things, the charging profile of the different chargers and the distribution efficiency.

Supplemental Tables to the Annual Energy Outlook 2012, US Energy Information Administration (EIA), Department of Energy, Washington, DC, June 2012. [↩]
D. Mead, “Top Five Electric Vehicle Initiatives of the Year,” Greentech Media, Dec. 8, 2011. [↩]
D. Karner, Clean Cities Webinar [Online]. Available at: http://www.theevproject.com/cms-assets/documents/70198-833686.clean-cities-webinar.pdf, June 25, 2012. [↩]
J. G. Kassakian, R. Schmalensee, T. D. Heidel, K. K. Afridi, D. J. Perreault, S. J. Gunter, et al., The Future of the Electric Grid, Cambridge: Massachusetts Institute of Technology, Dec. 2011. [↩]

High-efficiency Resonant dc/dc Converter Utilizing a Resistance Compression Network

Authors: W. Inam, K. K. Afridi and D. J. Perreault
Sponsorship: Masdar Institute

This project presents a new topology for a high-efficiency dc/dc resonant power converter that utilizes a resistance compression network^[1],^[2]. Unfortunately, while many soft-switched resonant designs achieve excellent performance for nominal operating conditions, performance can degrade quickly with variation in input and output voltages and power levels. The proposed topology seeks to overcome this challenge.

Experimental results from a 200 W prototype operating at 500 kHz show that high efficiency is maintained over a wide input voltage, output voltage and power range. As shown in Fig. 2 over 95% efficiency is maintained across an input voltage range of 25 V to 40 V with an output voltage of 400 V. These experimental results demonstrate the effectiveness of the proposed design.

: Figure 1: Topology of the proposed resistance compression network converter.

: Figure 2: Measured efficiency and output power versus input voltage variation (with output voltage at 400V).

Y. Han, O. Leitermann, D. A. Jackson, J. M. Rivas, and D. J. Perreault, “Resistance Compression Networks for Radio-Frequency Power Conversion,” IEEE Transactions on Power Electronics, Vol. 22, No.1, pp. 41-53, Jan. 2007. ) to provide simultaneous zero voltage switching and near-zero current switching across a wide range of input and output voltages and power levels. The resistance compression network maintains desired current waveforms over a wide range of voltage operating conditions. The use of on/off control in conjunction with narrowband frequency control enables high efficiency to be maintained across a wide range of power levels. The converter implementation provides galvanic isolation and enables large (greater than 1:10) voltage conversion ratios, making the system suitable for large step-up conversion in applications such as distributed photovoltaic converters.

Soft-switched resonant converter topologies providing zero-voltage switching (ZVS) or zero-current switching (ZCS) can greatly reduce loss at the switching transitions, enabling high efficiency at high frequencies ((R. L. Steigerwald, “High-Frequency Resonant Transistor DC-DC Converters,” IEEE Transactions on Industrial Electronics, vol. IE-31, no. 2, pp. 181-191, May 1984. [↩]
R. L. Steigerwald, “A Comparison of Half-Bridge Resonant Converter Topologies,” IEEE Transactions on Power Electronics, vol. 3, no. 2, pp. 174-182, Apr. 1988. [↩]

Two-stage Power Conversion Architecture for an LED Driver Circuit

Authors: S. Lim, J. Ranson, D. Otten, D. J. Perreault
Sponsorship: ARPA-E

LED lighting promises unprecedented reductions in energy consumption, but it comes with an as-yet unmet demand for high power density, high efficiency, and high-power-factor LED drivers^[1]. Considering a group of commercial line-interfaced LED drivers in the output power range of 3-30 W, we have found efficiencies in the range of 64-83% and power factors of 0.59-0.96, with no systems achieving both high efficiency and a high power factor. The switching frequencies of these drivers were in the range of 57-104 kHz, with correspondingly low power densities below 5 W/in³. The size of these drivers was uniformly dominated by magnetic components, and in each case the driver represented a major contribution to overall system size. It may be concluded that power conversion electronics continue to represent a major limitation in solid-state lighting, and that significant improvements in driver efficiency, power density and power factor will be necessary to meet market needs.

We introduce a merged-two-stage circuit topology and associated circuit design and controls to address these challenges. The proposed approach is suitable for efficient LED drivers operating from either a wide-range dc input voltage or an ac line voltage. This two-stage topology is based on a soft-charged switched-capacitor pre-regulator/transformation stage and a high-frequency magnetic regulator stage. Soft charging in the switched capacitor circuit, zero voltage switching in the high-frequency regulator circuit, and time-scale controls are used to maintain high efficiency, high power density, and a high power factor. Two implementations of the proposed architecture are demonstrated: a wide input voltage range dc-dc converter and a line interfaced ac-dc converter. The dc-dc converter shows 85-95% efficiency at 20W power across 25-200V input voltage range, and the ac-dc converter achieves 88% efficiency with 0.93 power factor at 8.4W average power^[2]^[3]^[4]^[5]^[6]^[7]^[8].

: Figure 1: Block diagram of the merged-two-stage conversion system.ottom): 100mA/div).

: Figure 2: Experimental measurement of input voltage and current waveforms from ac-line operation line (x: 5ms/div (top): 150V/div, (bottom): 100mA/div).

“Multi-year program plan fy09-fy14: Solid-state lighting research and development,” Office of Energy Efficiency and Renewable Energy, US Dept. of Energy by Navigant Consulting, Radcliffe Advisors, and SSLS, 2008. [↩]
D. Perreault, J. Hu, J. Rivas, Y. Han, O. Leitermann, R. Pilawa-Podgurski, A. Sagneri, and C. Sullivan, “Opportunities and challenges in very high frequency power conversion,” in Applied Power Electronics Conference and Exposition, APEC 2009. Feb. 2009, pp. 1 –14. [↩]
J. Hu, “Design of low-voltage, high-bandwidth radio-frequency power converters,” Ph.D. dissertation, Massachusetts Institute of Technology, Cambridge, 2012. [↩]
M. Seeman and S. Sanders, “Analysis and optimization of switched capacitor dc-dc converters,” Power Electronics, IEEE Transactions on, vol. 23, no. 2, pp. 841 –851, Mar. 2008. [↩]
R. Pilawa-Podgurski, D. Giuliano, and D. Perreault, “Merged two stage power converter architecture with soft charging switched-capacitor energy transfer,” in 39th IEEE Power Electronics Specialists Conference, 2008. [↩]
R. Pilawa-Podgurski and D. Perreault, “Merged two-stage power converter with soft charging switched-capacitor stage in 180 nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 47, no. 7, pp. 1557-1567, 2012. [↩]
R. Pilawa-Podgurski and D. Perreault, “Merged two-stage power converter with soft charging switched-capacitor stage in 180 nm CMOS,” in ESSCIRC 2011, Sept. 2011, pp. 479–482. [↩]
M. Seeman and S. Sanders, “Analysis and optimization of switched capacitor dc-dc converters,” in IEEE Computers in Power Electronics Workshop, 16-19 July 2006, pp. 216–224. [↩]

Efficient, Reliable Energy Buffer for Grid-interface Power Conversion with Switched Capacitor Architecture

Authors: M. Chen, K. K. Afridi, D. J. Perreault

A buffering strategy that utilizes the ability of a capacitor to efficiently operate over a wide voltage range allows increasing of the effective energy storage density to match that of an electrolytic capacitor^[1]^[2]^[3]. Previous switched capacitor buffering strategies have been shown to be effective in achieving high capacitor energy utilization; however, they are either too complicated for practical implementation or suffer a large voltage ripple ratio^[4]^[5]. This abstract presents a stacked switched capacitor (SSC) energy buffer architecture and some of its topological embodiments, which when used with longer life film capacitors overcome this limitation while achieving effective energy densities comparable to electrolytic capacitors. The architectural approach is introduced along with design and control techniques. A prototype SSC energy buffer using film capacitors, designed for a 320-V dc bus and able to support a 135-W load, has been built and tested with a power factor correction circuit. It is shown that the SSC energy buffer can successfully replace limited-life electrolytic capacitors with much longer life film capacitors while maintaining volume and efficiency at a comparable level. There are many possible implementations of the SSC energy buffer, enabling tradeoffs between complexity and performance^[6]^[7]^[8]^[9]. The optimal choice of the circuit topology depends on the dc bus voltage levels and the voltage ripple ratios of the specific applications. As technology evolves, the size and cost of both semiconductor switches and controls continue to reduce, yielding a further benefit of the SSC energy buffer architecture.

: Figure 1: Circuit diagram of a 1-2 unipolar stacked switching capacitor energy buffer.

: Figure 2: Relative size of passive energy storage components in different energy buffer architectures.

B. J. Pierquet and D. J. Perreault, “Single-Phase Photovoltaic Inverter Topology with Series-Connected Power Buffer,” Proceedings of IEEE Energy Conversion Congress and Exposition (ECCE), Sep. 2010. [↩]
A. C. Kyritsis and E. C. Tatakis, “A Novel Parallel Active Filter for Current Pulsation Smoothing on Single Stage Grid-Connected AC-PV Modules,” Proceedings of the 11th European Conference on Power Electronics and Applications (EPE), Aalborg, Denmark, Sep. 2007. [↩]
T. Shimizu, K. Wada and N. Nakamura, “Flyback-Type Single-Phase Utility-Interactive Inverter With Power Pulsation Decoupling on the DC Input for an AC Photovoltaic Module System,” IEEE Transactions on Power Electronics, vol. 21, no. 5, pp. 1264-1272, Sep. 2006. [↩]
S. Sugimoto, S. Ogawa, H. Katsukawa, H. Mizutani, and M. Okamura, “A Study of Series-Parallel Changeover Circuit of a Capacitor Bank for an Energy Storage System Utilizing Electric Double-layer Capacitors,” Electrical Engineering in Japan, vol. 145, pp. 33-42, 2003 [↩]
X. Fang, N. Kutkut, J. Shen, and I. Batarseh, “Ultracapacitor Shift Topologies with High Energy Utilization and Low Voltage Ripple,” International Telecommunications Energy Conference (INTELEC), Orlando, FL, Jun. 2010. [↩]
M. Chen; Afridi, K.K.; Perreault, D.J., “Stacked Switched Capacitor Energy Buffer Architecture,” IEEE Transactions on Power Electronics, vol.28, no.11, pp.5183,5195, Nov. 2013. [↩]
M. Chen, Stacked Switched Capacitor Energy Buffer Architecture, Master’s thesis, Massachusetts Institute of Technology, Cambridge, 2011. [↩]
M. Chen, K. K. Afridi, and D. J. Perreault, “Stacked Switched Capacitor Energy Buffer Architecture,” Proceedings of the IEEE Applied Power Electronics Conference (APEC), Orlando, FL, Feb. 2012. [↩]
K. K. Afridi, M. Chen, and D. J. Perreault, “Enhanced Bipolar Stacked Switched Capacitor Energy Buffers,” Proceedings of the IEEE Energy Conversion Congress and Exposition (ECCE), pp. 4209-4216, Raleigh, NC, Sep. 2012. [↩]

MTL Annual Research Report 2013