All entries for judy l. hoyt

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Gate-last Process for Strained-Ge p-MOSFETs with a High-k/Metal Gate Stack

• Authors: E. A. Polyzoeva, J. L. Hoyt, D. A. Antoniadis
• Sponsorship: SRC/FCRP MSD

Strained-Ge MOSFETs with significantly enhanced mobility compared to Si/SiO₂ hole mobility have previously been reported by our group (see Figure 1).  To enable use of these enhanced channel materials in future nanoscale gate-length FETs, the equivalent oxide thickness (EOT) must be scaled, and improved dielectric/semiconductor interface properties are required. In the search for  suitable gate dielectrics for use with Ge, bilayer dielectric systems have been investigated.  The bottom layer in these systems is expected to provide a high-quality interface to the semiconductor while the top layer is a high-k dielectric used to reduce the overall EOT and gate leakage of the structure.  An Al₂O₃/TiO₂ dielectric system with a sub-nm EOT and low density of interface states on bulk Ge wafers has been demonstrated ^[1] , and its implementation with strained-Ge devices is the aim of this work. Due to the limited thermal budget associated with the bilayer dielectric/metal gate stack, a gate-last process is developed.

In the gate-last process, the source and drain regions are activated before the gate dielectric and gate metal are deposited.  This is done to improve device reliability and mobility at scaled EOT, which can be significantly degraded when the high-k dielectric has gone through the high-temperature steps. Figure 2 shows the schematic gate-last process flow as well as the mask layout of the designed MOSFET structure. The preliminary experiments on gate-last Si MOSFETs show a superior interface quality compared to gate-first devices, a promising result in favor of gate-last strained-Ge MOSFETs, at least as a means of studying the dielectric/semiconductor interface.



Figure 1: Hole mobility of previously fabricated strained-Ge devices with and without a Si cap with enhancement factors up to 4.7x compared to universal Si/SiO2 hole mobility. The inset shows the cross section of the capped device. An increase in the enhancement factor is expected for an improved dielectric/semiconductor interface offered by the bilayer dielectric system.



Figure 2: Schematic gate-last process flow and mask layout of the MOSFET structure. The S/D regions are activated prior to gate dielectric/metal gate deposition to avoid high-k degradation during the high-temperature step.




1. S. Swaminathan. M.  Shandalov, Y.  Oshima, and P. C.  McIntyre, “Bilayer metal oxide gate insulators for scaled Ge-channel metal-oxide-semiconductor devices,” Applied Physics Letters, vol. 96, no. 8, pp. 082904-082904-3, Feb. 2010. [↩]

Asymmetrically Strained Si/Strained Ge Trigate p-MOSFETs

• Authors: W. Chern, P. Hashemi, J. L. Hoyt
• Sponsorship: SRC/FCRP MSD

Uniaxial strained Ge “nanobars” are of interest for future sub-10nm gate length p-MOSFETs because of the excellent electrostatic control afforded by the non-planar device geometry and the potential for high hole velocity in the uniaxial strained Ge.  In this work, asymmetrically strained Si/strained Ge trigate p-MOSFETs were fabricated from a strained germanium directly on insulator (SGDOI) substrate.  The SGDOI substrate was fabricated using a bond and etchback technique that is depicted in Figure 1.  An epitaxial wafer containing the desired final layers was bonded to a thermally oxidized Si handle wafer.  The bonded wafer stack is then mechanically ground and chemically etched, leaving the desired final structure with the original grown-in strain intact.  The wafer is processed to form p-MOSFETs using hybrid e-beam and photo-lithography to pattern nanobars and source/drain pads, resulting in the final structure seen in the inset of Figure 2.  The new free surfaces of the nanobars allow the originally biaxial strain to relax, causing asymmetric strain in the channel of the Ge trigate p-MOSFET.  The gate oxide was formed by flowing ozone for passivation and depositing 40A HfO₂ and 200A WN as the gate electrode.  The gate was used as a mask for ion implantation of boron, and standard CMOS processes was used for metallization. Figure 2 shows the transfer characteristics of a p-MOSFET with 18-nm-wide nanowires.



Figure 1: Schematic of the bond and etchback process for the SGDOI substrate fabrication. After bond and etchback, the film is patterned into a nanobar to induce the biaxial to uniaxial strain transformation.



Figure 2: Transfer characteristics of a strained-Ge trigate with 500, 18nm-wide nanowires in parallel and a gate length of 10um. The sweeps are -50mV (black) and -1V (red). The SS for the device is 83mV/dec, and the hysteresis is ~40mV. The inset illustrates the device schematic.




1. P. Hashemi, L. Gomez, M. D. Robertson, M. Canonico, and J. L. Hoyt, “Asymmetric strain in nanoscale patterned strained-Si/strained-Ge/strained-Si heterostructures on insulator,” Applied Physics Letters, vol. 90, no. 8, p. 083109, Aug. 2007.

MOS Capacitance-Voltage Method for InAs/GaSb Band Alignment Extraction

• Authors: J. T. Teherani, D. A. Antoniadis, J. L. Hoyt

Significant reduction in processor power is needed in order to sustain future data center growth and extend battery life of mobile devices. To this end, we are investigating tunneling field-effect transistors (TFETs) ^[1] as a new type of switch that could potentially provide a subthreshold swing (SS) lower than 60 mV/decade at room temperature, which would enable low power, energy efficient devices.

The structure and energy band diagram of an InAs/GaSb TFET are shown in Figure 1a and 1b, respectively. The TFET switches by modulating the electron tunneling current that flows from the GaSb valence band to the InAs conduction band through the application of a gate voltage that bends the bands. Quantum mechanical tunneling depends strongly on the effective band gap, E_G,eff, the energy difference between the InAs conduction band and the GaSb valence band at the InAs/GaSb interface, as indicated in Figure 1b. Since tunneling current is exponentially dependent on the effective band gap, characterizing the band alignment of the InAs/GaSb heterojunction is critical for optimal device design.

Figure 2 shows a simulated quasi-static capacitance-voltage curve of an ideal InAs/GaSb MOS-capacitor. Structure and material parameters (such as band alignment of the InAs/GaSb heterojunction) that affect specific regions of the capacitance-voltage curve are labeled in the figure. These parameters can be extracted by fitting quasi-static quantum mechanical simulations to experimentally measured capacitance-voltage data using a technique that was used successfully in the study of band alignments in the Si-Ge material system ^[2] . Additionally, a new technique has also been developed to properly model the density of interface traps (D_it) at the dielectric/InAs interface.



Figure 1: (a) TFET device structure. (b) Energy band diagram along the line indicated in (a). Electrons from the GaSb valence band tunnel into the InAs conduction band when a sufficient positive gate bias is applied. E_G,eff  is the difference in energy between the InAs conduction band and the GaSb valence band.



Figure 2: Simulated quasi-static capacitance-voltage curve of an ideal InAs/GaSb heterostructure MOS-capacitor with no interface traps. The peak capacitance at negative voltage provides the equivalent oxide thickness (EOT), and is related to the width between the accumulation and inversion regimes of the CV. As E_G,eff  becomes smaller, so too does the width between the regimes. The detailed shape of the capacitance-voltage curve for positive voltages is due to electron sub-bands in the InAs layer and will likely be obscured by D_it  in the experimental measurement.




1. A. C. Seabaugh and Qin Zhang, “Low-Voltage Tunnel Transistors for Beyond CMOS Logic,” Proceedings of the IEEE, vol. 98, no. 12, pp. 2095–2110, 2010. [↩]
2. S. P. Voinigescu, K. Iniewski, R. Lisak, C. A. T. Salama, J.-P. Noél, and D. C. Houghton, “New technique for the characterization of Si/SiGe layers using heterostructure MOS capacitors,” Solid-State Electronics, vol. 37, no. 8, pp. 1491–1501, Aug. 1994. [↩]

MOS Interfaces in the InAs/GaSb System

• Authors: T. Yu, J. L. Hoyt
• Sponsorship: NSF

With the rapid downscaling of CMOS technology, III-V materials have gained much attention due to their high electron mobility. In particular, indium-arsenide and gallium-antimonide are becoming more popular due to their matched lattice constant and their complimentary physical properties, such as bandgap and carrier mobility ^[1] ; various heterostructure-based high performance field-effect transistors (FET) and tunneling transistors have been proposed ^{[1] [2]} . On the other hand, this material system faces challenges due to the poor oxide/semiconductor interface, which results in high interface trap concentration (D_it) and hence Fermi-level pinning ^{[3] [4]} . Therefore, understanding the metal-oxide-semiconductor (MOS) interface in this material system is critical. This study investigates atomic-layer-deposited (ALD) Al₂O₃ on InAs to provide a preliminary understanding of the Al₂O₃/InAs interface.

On an S-doped n-type InAs substrate, 60 cycles of Al­₂O₃ are deposited at 200°C and 250°C after HCl wet chemical cleaning. Then, a Mo/Pt/Au (30 nm/20 nm/100 nm) gate stack is formed using electron-beam evaporation; the back contact is formed using Ti/Au. Finally, 30s post-metallization annealing in N₂ is carried out. Figure 1 shows the normalized capacitance-voltage (C-V) curves of both samples with frequencies varied from 10kHz to 1MHz. The depletion region of the C-V curve is not sharp and deep, as predicted by simulations ^[5] , which is mainly due to the series capacitance corresponding to D_it. Still, the comparison between the two samples shows that Al­₂O₃ deposited at 200°C yields lower D_it than 250°C. Figure 2 plots the C-V hysteresis of the two samples at 100kHz, which reflects the oxide mobile charge near the interface. The results show that the hysteresis is moderate for both samples and that the ALD dielectric quality is promising. Quantitative analysis of the D_it is ongoing.  In summary, InAs/GaSb is a promising heterojunction system, and research is needed to better understand and optimize the dielectric/semiconductor interface.



Figure 1: C-V curves of InAs MOSCAP with Al2O3 dielectric deposited at 200°C and 250°C. Higher deposition temperature gives slightly higher dielectric constant of the dielectric. Impact of Dit induced series capacitance dominates the depletion behavior of both samples.



Figure 2: Hysteresis in C-V characteristics of both samples at 100KHz. Mobile charge control in both samples is promising, with hysteresis ~100mV.




1. H. Kroemer, “The 6.1 Å family (InAs, GaSb, AlSb) and its heterostructures: A selective review,” Physica E: Low-dimensional Systems and Nanostructures, vol. 20, no. 3–4, pp. 196–203, Jan. 2004. [↩] [↩]
2. B. R. Bennett, R. Magno, J. B. Boos, W. Kruppa, and M. G. Ancona, “Antimonide-based compound semiconductors for electronic devices: A review,” Solid-State Electronics, vol. 49, no. 12, pp. 1875–1895, Dec. 2005. [↩]
3. H.-D. Trinh, E. Y. Chang, Y.-Y. Wong, C.-C. Yu, C.-Y. Chang, Y.-C. Lin, H.-Q. Nguyen, and B.-T. Tran, “Effects of wet chemical and trimethyl aluminum treatments on the interface properties in atomic layer deposition of Al₂O₃ on InAs,” Japanese Journal of Applied Physics, vol. 49, no. 11, p. 111201, Nov. 2010. [↩]
4. H.-Y. Lin, S.-L. Wu, C.-C. Cheng, C.-H. Ko, C. H. Wann, Y.-R. Lin, S.-J. Chang, and T.-B. Wu, “Influences of surface reconstruction on the atomic-layer-deposited HfO₂/Al₂O₃/n-InAs metal-oxide-semiconductor capacitors,” Applied Physics Letters, vol. 98, no. 12, p. 123509, 2011. [↩]
5. D. Wheeler, L.-E. Wernersson, L. Fröberg, C. Thelander, A. Mikkelsen, K.-J. Weststrate, A. Sonnet, E. M. Vogel, and A. Seabaugh, “Deposition of HfO2 on InAs by atomic-layer deposition,” Microelectronic Engineering, vol. 86, no. 7–9, pp. 1561–1563, Sep. 2009. [↩]

Judy L. Hoyt

• Title: Professor
• Department: Department of Electrical Engineering and Computer Science

Collaborators

• Dimitri Antoniadis, EECS
• Franz Kartner, EECS
• Jose Menendez, ASU
• Ammar Nayfeh, Masdar Institute
• Ted Lyszczarz, MIT Lincoln Labs
• Jung Yoon, MIT Lincoln Labs

Graduate Students

• Winston Chern, EECS
• Nicole DiLello, EECS
• Eva Polyzoeva, EECS (co-supervised with Prof. Dimitri Antoniadis)
• Jamie Teherani, EECS (co-supervised with Prof. Dimitri Antoniadis)
• Tao Yu, EECS

Research Staff

• Gary Riggott, Research Specialist
• Pouya Hashemi, Post-doctoral Scholar

Support Staff

• Lori McCormick, Administrative Assistant II

Publications

P. Hashemi and J.L. Hoyt, “High Hole-Mobility Strained-Ge/Si0.6 Ge0.4 P-MOSFETs With High-K/Metal Gate: Role of Strained-Si Cap Thickness,” IEEE Electron Device Letters, v 33, n 2, p 173-5, Feb. 2012.

S.A. Hadi, A. Nayfeh, P. Hashemi, and J.L. Hoyt, “a-Si/c-Si1-xGex/c-Si heterojunction solar cells,” in International Conference on Simulation of Semiconductor Processes and Devices, SISPAD, pp. 191-194, 2011.

S.A. Hadi, P. Hashemi, A. Nayfeh, and J.L. Hoyt, “Thin-Film a-Si/c-Si1-xGex/c-Si Heterojunction Solar Cells: Design and Material Quality Requirements,” ECS (Electrochemical Society) Transactions, Vol. 41 (4), pp. 3-14, 2011.

S. Paydavosi, K. Aidala, P. Brown, P. Hashemi, G. J. Supran, J. L. Hoyt, and V. Bulovic, “High-Density Charge Storage on Molecular Thin Films- Candidate Materials for High Storage Capacity Memory Cells,” IEEE International Electron Device Meeting (IEDM ’11), Washington DC, USA, December 2011.

(Invited) J. Hoyt, P. Hashemi, and W. Chern, “Strained Nanowire MOSFETs,” invited talk presented at the 220th Electrochemical Society (ECS), Session E9-ULSI Process Integration, Boston, Massachusetts, USA, October 2011.

(Invited) Pouya Hashemi, H.-S. Lee, M. A. Bhuiyan, D. A. Antoniadis, and J. L. Hoyt,  “High Mobility Strained Ge Channels and Gate Dielectrics for Planar and Non-Planar p-MOSFETs,” Mat. Res. Soc. Meeting, San Francisco, April 27, 2011.

N. A. DiLello and J.L. Hoyt, “Impact of post-metallization annealing on Ge-on-Si photodiodes passivated with silicon dioxide,” Appl. Phys. Lett. 99, 033508 (2011).

Khilo, A; Spector, S.J.; Grein, M.E.; Nejadmalayeri, A.H.; Holzwarth, C.W.; Sander, M.Y.; Dahlem, M.S.; Peng, M.Y.; Geis, M.W.; DiLello, N.A.; Yoon, J.U.; Motamedi, A.; Orcutt, J.S.; Wang, J.P.; Sorace-Agaskar, C.M.; Popovic, M.A.; Jie Sun; Gui-Rong Zhou; Hyunil Byun; Jian Chen; Hoyt, J.L.; Smith, H.I.; Ram, R.J.; Perrott, M.; Lyszczarz, T.M.; Ippen, E.P.; Kartner, F.X, “Photonic ADC: overcoming the bottleneck of electronic jitter”, Optics Express, v 20, n 4, p 4454-69, 21 Nov. 2011.

P. Hashemi, J.T. Teherani, and J.L. Hoyt, “Investigation of Hole Mobility in Gate-All-Around Si Nanowire p-MOSFETs with High-k/Metal-Gate: Effects of Hydrogen Thermal Annealing and Nanowire Shape,” International Electron De­vice Meeting (IEDM 2010), San Francisco, USA, Session 34.5 De­cember 2010.

P. Hashemi, C.D. Poweleit, M. Canonico, and J.L. Hoyt, “Ad­vanced Strained-Silicon and Core-Shell Si/Si1-xGex Nanowires for CMOS Transport Enhancement,” ECS (Electrochemical Society) Transactions, October 2010.

M. Kim, P. Hashemi, and J.L. Hoyt, Increased critical success for high Ge-content strained SiGe-on Si Using selective epitaxial growth, Appl. Phys. Lett. 97, 262106, 2010.

L. Gomez, C. Ni Chleirigh, P. Hashemi, and J.L. Hoyt, “En­hanced Hole Mobility in High-Ge Content Asymmetrically Strained-SiGe p-MOSFETs,” IEEE Electron Device Letters, vol. 31, no. 8, pp. 782 – 784, August, 2010.

Guangrui Xia and J.L. Hoyt, “Si-Ge interdiffusion under oxidizing con­ditions in epitaxial SiGe hetero­structures with high compressive stress,” Applied Physics Letters, v 96, n 12, p 122107 (3 pp.), 22 March 2010.

P. Hashemi, M. Kim, J. Hennessy, L. Gomez, D.A. Antoniadis and J.L. Hoyt, “Width-dependent hole mobility in top-down fabricated Si-core/Ge-shell nanowire MOS­FETs”, Appl. Phys. Lett. 96 (6), p. 063109, Feb. 2010.

J.S. Orcutt, A. Khilo, M.A. Popovic, C.W. Holzwarth, H. Li, J. Sun, B. Moss, M.S. Dahlem, E.P. Ippen, J.L. Hoyt, V. Stojanovic, F.X. Kärt­ner, H.I. Smith, and R.J. Ram, “Photonic integration in a commer­cial scaled bulk-CMOS process,” Source: 2009 International Confer­ence on Photonics in Switching, PS ’09, 2009, 2009 International Conference on Photonics in Switching, PS ’09, p. 2.