All entries for gallium nitride

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LED Lighting System using Gallium Nitride FETs

• Authors: S. Bandyopadhyay, F. Yaul, A. P. Chandrakasan
• Sponsorship: MIT GaN Energy Initiative

This work focuses on using gallium nitride (GaN) FETs for an LED lighting system. The idea is to utilize the favorable figure of merit provided by the GaN technology to miniaturize the magnetic components in the power converter by using high switching frequencies for the power converter. An LED driver application is chosen because the lighting industry is expected to see substantial growth in the near future with the advent of high-efficiency LEDs. This project will demonstrate a high-efficiency, small form factor LED lighting system with a long lifetime that can replace incandescent bulbs or CFLs. Efforts aim for design and implementation of high power density, off-line, high-frequency power conversion and control circuits.

The drivers are being implemented on a CMOS die. This will directly interface with discrete commercial GaN power devices. Circuits to perform power factor correction and dimming control are also being designed. Since the system will interface directly with the AC mains, an EMI filter is being used with the rectifier. Figure 1 shows the high-level block diagram of the system envisioned.



Figure 1: Block diagram of LED driver.

300-GHz GaN Transistors

• Authors: D. S. Lee, E. Matioli, T. Palacios
• Sponsorship: DARPA NEXT Program, NSF CAREER Award, ONR DURIP Program

The unique combination of high electron velocity and high breakdown voltage of GaN makes this material an ideal candidate for high power and high frequency applications. Among the different possible nitride structures, an InAlN/GaN heterostructure is one of the most promising candidates for high frequency applications because the large polarization discontinuity between InAlN and GaN induces an extremely large charge density with barriers thinner than 10 nm.

This work reports lattice-matched In_0.17Al_0.83N/GaN high electron mobility transistors (HEMTs) on a SiC substrate with a record current gain cutoff frequency (f_T) of 300 GHz [1-2]. To suppress short-channel effects (SCEs), an In_0.15Ga_0.85N back-barrier is applied in an InAlN/GaN heterostructure for the first time. The GaN channel thickness is also reduced to 26 nm, which allows a good immunity to SCEs for gate lengths down to 70 nm, even with a relatively thick top barrier (9.4-10.4 nm). In a device with a gate length (L_g) of 30 nm, an on-resistance (R_on) of 1.2 Ω•mm, and an extrinsic transconductance (g_m.ext) of 530 mS/mm, a peak f_T of 300 GHz is achieved. An electron velocity of 1.37-1.45×10⁷ cm/s is extracted by two different delay analysis methods.



Figure 1: (a) Cross-sectional schematic of an InAlN/GaN HEMT with an InGaN back-barrier. (b) I_ds-V_ds characteristics of the devices with L_g = 30 nm.






1. D. S. Lee, X. Gao, S. Guo, D. Kopp, P. Fay, and T. Palacios, “300-GHz InAlN/GaN HEMTs with InGaN back-barrier,” IEEE Electron Device Letters, vol. 32, no. 11, pp. 1525-1527, Nov. 2011.
2. D. S. Lee, B. Lu, M. Azize, X. Gao, S. Guo, D. Kopp, P. Fay, and T. Palacios, “Impact of GaN channel scaling in InAlN/GaN HEMTs,” IEDM Technical Digest 2011, pp. 457-460, Dec. 2011.

Technology Development for GaN and Si Integration

• Authors: Z. Liu, T. Palacios
• Sponsorship: Singapore-MIT Alliance for Research and Technology

GaN is an excellent material to be used in high-power, high-frequency and high-temperature applications due to its wide band gap, high saturation velocity, etc. The monolithic integration of GaN power and/or high frequency devices with Si CMOS digital ICs would enable a new level of circuit design flexibility ^[1] . However, typically the GaN device fabrication uses different process technologies from the standard CMOS technologies in Si foundries, such as the Au-contained ohmic process. To realize the target of GaN and Si CMOS integration, Si-CMOS compatible process technologies need to be developed. For the first step, we endeavor to find an Au-free ohmic contact recipe with low contact resistance and smooth metal surface.

The samples we used in this work have a 3-nm GaN cap, a 20-nm unintentionally doped AlGaN barrier layer, and a GaN buffer layer grown on a 6-inch Si wafer. Mesa isolation was realized using ICP systems with Cl₂/BCl₃ gases. For the ohmic contact, we tried different metal schemes including Ti/Al, Ti/Al/Ti, Ti/Al/Pt, Ti/Al/Ni/Pt, Ti/Ge/Ti/Al/Ni/Pt, Si/Ti/Al/Ti/Ta, Mo/Al/Mo/Ti, Ta/Al/Ta, Ta/Al/Ni/Ta, etc, with different annealing temperatures varying from 500°C to 975°C using rapid thermal annealing (RTA) in N₂ ambience. We also tried to include a shallow recess using low etch-rate SiCl₄ plasma etch in an ICP system to improve the ohmic contact. Among these recipes, the metal scheme of Ti/Al/Ni/Pt is found to give a relatively low contact resistance with very good metal surface. Lower ohmic contact resistance values together with a smooth metal surface can be obtained if a 20-30-nm recess is added.

Figure 1 shows the optical pictures of the ohmic metal surface after RTA for 30 s for metal schemes of Ti/Al/Ni/Au, Ti/Al/Ni/Pt, and Ti/Al/Ni/Pt with recess. The Au-contained recipe shows a very rough surface even it is annealed at a relatively low temperature of 800°C. The intermixing of Al and Au and the formation of viscous AlAu₄ phase are believed to result in the rough surface ^[2] . Without Au, the metal surface of Ti/Al/Ni/Pt is very smooth even it is annealed at a much high temperature up to 950°C. The recess of 20 nm (and 30 nm, not shown here) has no obvious effect on the metal surface after annealing. Figure 2 shows the typical contact resistance (R_C) values measured using the transition length method (TLM). A low R_C of around 0.45 Ω-mm can be obtained for the normal Ti/Al/Ni/Au recipe. The R_C value of Ti/Al/Ni/Pt metal is higher (~2.0 Ω-mm), and it can decrease to 1.6Ω-mm with the recess of 20 nm. In the future, more work needs to be carried out to further lower the R_C and optimize the Au-free ohmic contact recipes.



Figure 1: The optical pictures of ohmic metal surfaces for AlGaN/GaN HEMTs. (a) Ti/Al/Ni/Au with RTA at 800°C; (b) Ti/Al/Ni/Pt with RTA at 950°C; and (c) Ti/Al/Ni/Pt with 20-nm recess and RTA at 950°C.



Figure 2: TLM results of the ohmic contact for AlGaN/GaN HEMTs. (a) Ti/Al/Ni/Au with RTA at 800°C; (b) Ti/Al/Ni/Pt with RTA at 950°C; and (c) Ti/Al/Ni/Pt with 20-nm recess and RTA at 950°.




1. H. S. Lee, K. Ryu, M. Sun, and T. Palacios, “Wafer-level heterogeneous integration of GaN HEMTs on Si (100) MOSFETs,” IEEE Electron Device Letters, vol. 33, no. 2, pp. 200-202, Feb. 2012. [↩]
2. A. N. Bright, P. J. Thomas, M. Weyland, D. M. Tricker, C. J. Humphreys, and R. Davies, “Correlation of contact resistance with microstructure for Au/Ni/Al/Ti/AlGaN/GaN ohmic contacts using transmission electron microscopy,” Journal of Appl. Phys., vol. 89, no. 6, pp. 3143-3150, Mar. 2001. [↩]

GaN-Based Transistors for Power Electronic Applications

• Authors: D. Piedra, B. Lu, M. Sun, E. Matioli, H.-S. Lee, T. Palacios
• Sponsorship: MIT GaN Energy Center, ARPA-E ADEPT, DOE GIGA, SRC/FCRP MSD, SRC/FCRP IFC

Wide band-gap III-nitride semiconductors have great potential for the next generation of power electronics. GaN high-electron-mobility transistors (HEMTs) in particular have attracted great interest due to their high breakdown electric field and high electron mobility. With lower conduction loss and higher switching frequency, GaN-based transistors can improve the efficiency and reduce the size of many power electronics systems.

The standard AlGaN/GaN HEMTs are depletion-mode transistors. However, normally-off transistors are preferred in power electronics. Recently, our group has developed a new normally-off tri-gate GaN metal-insulator-semiconductor-field-effect-transistor (MISFET) ^[1] . By using a three-dimensional tri-gate structure and a sub-micron gate recess, we achieve high performance normally-off GaN transistors with a breakdown voltage as high as 565 V at a drain leakage current of 0.6 μA/mm. The new tri-gate normally-off GaN MISFET has a maximum current density of 530 mA/mm and an on/off current ratio of more than 8 orders of magnitude with a sub-threshold slope of 86±9 mV/decade, as Figure 1 shows. We have also demonstrated a new multi-finger technology with higher yield and lower device resistance for InAlN/GaN HEMTs. A multi-finger device with gate width of 39.6 mm has an on-resistance (R_on) of 0.244 Ω and a maximum current of 18.5 A, as in Figure 2(a).

Finally, ion-implantation isolation technology has also been developed. A state-of-the-art 1800 V breakdown voltage with 2.2 mΩcm² specific on-resistance has been achieved on AlGaN/GaN HEMTs on Si substrate (Figure 2(b)). Devices with ion-implantation isolation have higher breakdown voltage than devices using mesa-etching isolation, showing that ion-implantation isolation is a promising candidate for the next-generation high voltage GaN-based HEMT fabrication.



Figure 1: (a) Transfer characteristics of a tri-gate normally-off GaN MISFET and a standard planar-gate D-mode GaN MIS-HEMT. Both devices have L_gs = 1.5 μm, L_g = 2 μm, L_gd = 10 μm and W = 100 μm. (b) Three-terminal breakdown voltage (BV) measurement of the tri-gate normally-off GaN MISFET with L_gd = 10 μm at V_gs = 0 V.



Figure 2: (a) I_d-V_d characteristic of a multifinger device with W_g = 39.6 mm and R_on = 0.244 Ω. (b) Three-terminal breakdown voltage as a function of L_gd for implantation and mesa devices. The inset shows the breakdown voltage at leakage current of 10 μA/mm




1. B. Lu, E. Matioli and T. Palacios, “Tri-gate normally-off GaN power MISFET,” IEEE Electron Device Letters, vol. 33, no. 3, pp. 360-362, 2012. [↩]

Reliability Studies of AlGaN/GaN HEMTs

• Authors: S. C. Tan, F. Gao, J. Joh, L. Li, T. Palacios, J. A. del Alamo, C. V. Thompson, S. C. Tan, F. Gao, J. Joh, L. Li, T. Palacios, J. A. del Alamo, C. V. Thompson

There is an increasing interest in AlGaN/GaN high electron mobility transistors (HEMTs) due to their great potential for high performance at microwave frequencies. However, the performance of these devices is often limited by material reliability issues. Unfortunately, a detailed physical understanding of the degradation mechanisms is still lacking. The objective of this project is to develop that understanding through appropriate testing and failure analysis, so that test methods and models can be developed that will lead to further improvement in the reliability and electrical performance of these devices though optimization their design.



Figure 1: Pits and particles observed at the gate edges of a stressed AlGaN HEMT (top view) ^[1] .

Recent work has focused on the formation of pits at the edge of the gate contact during electrical stressing and performance degradation ^{[1] [2] [3]} . These pits have been observed to form under a variety of stressing conditions and in a range of temperatures.  We have found that in some cases the pits are associated with formation of particles that appear to be an oxide of Ga (Figure 1), and that pit and particle formation is suppressed when samples are properly passivated or when they are stressed in ultra-high vacuum conditions. Also, stressing in the presence of water vapor was found to enhance the rate of degradation ^[1] .  This suggests that this failure mechanism is associated with electrochemically-enhanced oxidation.  We have also observed that the rate of pit formation is affected by temperature, both in isothermal experiments and in experiments in which the temperature within an individual device varies significantly.  This finding indicates that this failure process is thermally activated. We estimate an activation energy of about 0.3eV ^[2] .

Analytical techniques such as scanning electron microscopy (SEM), transmission electron microscopy (TEM), atomic force microscopy (AFM), cathode luminescence (CL), and energy-dispersive X-ray spectroscopy (EDX) will be employed in future studies of this and other degradation processes, with the goal of developing predictive models for failure rates and reliability.

1. P. Makaram, J. Joh, J. A. del Alamo, T. Palacios, and C. V. Thompson, “Evolution of structural defects associated with electrical degradation in AlGaN/GaN high electron mobility transistors,” Appl. Phys. Lett,  Vol. 96, p. 233509, 2010. [↩] [↩] [↩]
2. F. Gao, B. Lu, L. Li, S. Kaun, J. S. Speck, C. V. Thompson, and T. Palacios, “Role of oxygen in the OFF-state degradation of AlGaN/GaN high electron mobility transistors,” Appl. Phys. Lett., vol. 99, p. 223506, 2011. [↩] [↩]
3. L. Li, J. Joh, J. A. del. Alamo, and C. V. Thompson,“Spatial distribution of structural degradation under high-power stress in AlGaN/GaN HEMTs,” Appl. Phys. Lett., to be published. [↩]

Impact of Metal-induced Strain in InAlN/GaN Nanoribbons

• Authors: M. Azize, O. I. Saadat, T. Palacios
• Sponsorship: ONR, NSF

Nitride transistors with current gain cut-off frequencies (f_T) of 300 GHz and power gain cut-off frequencies (f_max) of 394 GHz have been reported ^{[1] [2]} . However, the frequency performance of these devices is still far from the theoretical limit due to poor gate modulation efficiency, short channel effects, high access resistances (R_a), and specific contact resistance (r_c). Nanoribbon (NR)-based nitride HEMTs could overcome many of these limitations by improving the electron confinement thanks to the excellent electrostatics of wrap-around gates ^[3] . Moreover, strong piezoelectric-induced doping can be generated in NR nitride-based semiconductors and increase the maximum operating frequency of nitride devices by reducing the parasitic resistances (Ra and r_c). In this project, we study the use of Ti-induced strain in InAlN/GaN NR HEMTs.

 NR and planar devices are fabricated on the same chip. A Ti/Al/Ni/Au metal stack is then deposited for ohmic contact formation. Electron beam lithography and dry etching are performed in some devices to define NR structures between the ohmic contacts with widths (w) in the w~20-90 ± 10 nm range and a period (p) of p~135 ± 10 nm. An additional Ti strip was deposited between the ohmic contacts (cf. inset of Figure 2) with a width of ~100 mm and a length varying from ~2 to 16 mm and annealed at 870 ^◦C for 30 s in N₂ environment. Figure 1 shows the total resistance R_T in NR and planar devicesas a function of the area coverage of the Ti stripes. A quasi-linear R_T decrease is observed when the Ti surface area increases in the InAlN/GaN NRs samples, unlike in the planar device. The mechanical stress introduced by Ti stripes has a strong effect on the transport properties of InAlN/GaN NRs. Figure 2 shows the decrease of the sheet resistance (R_shTi) underneath the Ti stripe in InAlN/GaN NRs as a function of NR widths. The R_shTi in the NR and planar devices is decreased by ~50-75 % and ~10%, respectively.



Figure 1: Total resistance in InAlN/GaN channel as a function of the area coverage of the Ti stripes. The inset shows a cartoon of NR and planar devices with different area coverage of the Ti stripes.



Figure 2: Sheet resistance underneath of the Ti metal stripes in InAlN/GaN devices as a function of the NR width. The inset shows a cartoon of NR and planar devices with identical area coverage of the Ti stripes.




1. D. S. Lee, X. Gao, S. Guo, D. Kopp, P. Fay, and T. Palacios, “300-GHz InAlN/GaN HEMTs with InGaN back barrier, IEEE Electron Device Lett., to be published. [↩]
2. K. Shinohara, D. Regan, I. Milosavljevic, A. L. Corrion, D. F. Brown, P. J. Willadsen, C. Butler, A. Schmitz, S. Kim, V. Lee, A. Ohoka, P. M. Asbeck, and M. Micovic, “Electron velocity enhancement in laterally scaled GaN DH-HEMTs with f_T of 260 GHz,” IEEE Electron Device Lett., vol. 32, no. 8, pp. 1074-10176, Aug. 2011. [↩]
3. W. Lu, P. Xie, and C. M. Lieber, “Nanowire transistor performance,” IEEE Trans. Electron Dev., vol. 55, no 11, pp 2859-2876, Nov. 2008. [↩]

Use of in-situ SiN_x to Reduce the OFF-state Degradation of AlGaN/GaN HEMTs

• Authors: F. Gao, S. Keller, U. K. Mishra, C. V. Thompson, T. Palacios
• Sponsorship: ONR DRIFT-MURI

Thanks to their excellent electrical performance, AlGaN/GaN high electron mobility transistors (HEMTs) are considered ideal devices for the next generation of high-power and high-frequency electronics ^[1] . However, the limited understanding of their long-term reliability and degradation mechanisms is slowing down the insertion of these devices in actual systems ^[2] .

Recently, we have reported the formation of oxide particles next to the gate edge of GaN HEMTs after OFF-state step-stress degradation experiments ^[3] . Underneath these particles, pits similar to the ones reported in previous papers ^[4] are observed. In this work, we investigate the role of oxygen in the formation of these particles/pits during OFF-state stress and use oxygen diffusion barriers to improve the reliability of AlGaN/GaN HEMTs.

Two different dielectrics have been used: Al₂O₃ deposited by atomic layer deposition and in-situ SiN_x deposited immediately after the growth of the AlGaN/GaN epitaxial layer by metal organic chemical vapor deposition (MOCVD). Step-stress degradation experiments were performed in both samples in air and vacuum. No degradation was found in either sample during the experiments in vacuum, which shows that the oxygen necessary for the particle formation probably comes from air. In contrast, when the samples were stressed in air, a large degradation and particle/pit formation were found in the Al₂O₃-passivated sample, while no structural or electrical degradation was found in the sample with in-situ SiN_x (see Figures 1 and 2). The in-situ SiN_x dielectric is believed to be a much better diffusion barrier for oxygen gas and water vapor than Al₂O₃, which significantly reduces device degradation.

In summary, the in-situ deposition of a SiN_x gate dielectric and passivation layer successfully eliminated the diffusion of oxygen from air and water vapor to the AlGaN surface, which improved the OFF-state reliability of AlGaN/GaN HEMTs.



Figure 1: Transfer characteristics of the device with ALD Al₂O₃ gate dielectric stressed at V_gs = -100 V and V_ds = 0 V for 6000 s in air and in vacuum. Permanent degradation of the drain current is observed in air.



Figure 2: Transfer characteristics of the device with in-situ SiN_x gate dielectric stressed at V_gs = -100 V and V_ds = 0 V for 6000 s in air. No current degradation is observed.




1. U. K. Mishra, L. Shen, T. E. Kazior, and Y-F Wu, Proceedings of the IEEE, 2008, vol. 96, p. 287. [↩]
2. G. Meneghesso, G. Verzellesi, F. Danesin, F. Rampazzo, F. Zanon, A. Tazzoli, M. Meneghini, and E. Zanoni, IEEE Trans. Device Mater. Reliab. vol. 8, p. 332, 2008. [↩]
3. F. Gao, B. Lu, L. Li, S. Kaun, J. S. Speck, C. V. Thompson, and T. Palacios, Appl. Phys. Lett. vol. 99, p. 223506, 2011. [↩]
4. J. Joh and J. A. del Alamo, IEEE Electron Device Lett. vol. 29, p. 287, 2008. [↩]