All entries for Hae-Seung Lee

• Print This Page
• Download as PDF

Center for Integrated Circuits & Systems

• Leadership: Professor Hae-Seung Lee, Director

The Center for Integrated Circuits and Systems (CICS) at MIT, established in early 1998, is an industrial consortium created to promote new research initiatives in circuits and systems design, as well as to promote a tighter technical relationship between MIT’s research and relevant industry. Seven faculty members participate in the CICS: Hae-Seung Lee (director), Duane Boning, Anantha Chandrakasan, Joel Dawson, David Perreault, Charles Sodini, and Vladimir Stojanovic. CICS investigates a wide range of circuits and systems, including wireless and wireline communication, high-speed and RF circuits, microsensor/actuator systems, imagers, digital and analog signal processing circuits, and power conversion circuits, among others.

We strongly believe in the synergistic relationship between industry and academia, especially in practical research areas of integrated circuits and systems. CICS is designed to be the conduit for such synergy. At present, participating companies include Analog Devices, IBM, Linear Technology, Marvell Technology Group, Maxim Integrated Products, Media Tek, National Semiconductor, and Texas Instruments.

CICS’s research portfolio includes all research projects that the seven participating faculty members conduct, regardless of source(s) of funding, with a few exceptions.

Technical interaction between industry and MIT researchers occurs on both a broad and individual level. Since its inception, CICS recognized the importance of holding technical meetings to facilitate communication among MIT faculty, students, and industry.  We hold two informal technical meetings per year open to CICS faculty, students, and representatives from participating companies. Throughout each full-day meeting, faculty and students present their research, often presenting early concepts, designs, and results that have not been published yet. The participants then offer valuable technical feedback, as well as suggestions for future research.  More intimate interaction between MIT researchers and industry takes place during work on projects of particular interest to participating companies. Companies may invite students to give on-site presentations, or they may offer students summer employment. Additionally, companies may send visiting scholars to MIT or enter into a separate research contract for more focused research for their particular interest.. The result is truly synergistic, and it will have a lasting impact on the field of integrated circuits and systems.

Hae-Seung Lee

• Title: ATSC Professor of Electrical Engineering and Computer Science and Director, Center for Integrated Circuits and Systems
• Department: Department of Electrical Engineering and Computer Science

Graduate Students

• A. Chang, Res. Asst., EECS
• A. C.-H. Chow, Res. Asst., EECS
• Y. J. Chu, Res. Asst., EECS
• M. Guyton, Res. Asst., EECS
• D. Kumar, EECS
• P. Lajevardi, Res. Asst., EECS
• S. Lee, Res. Asst., EECS
• M. Markova, Res. Asst., EECS
• S. Pietrangelo, EECS
• D. Y. Yoon, Res. Asst., EECS

Support Staff

• C. Collins, Assistant to Director of Center for Integrated Circuits and Systems

Publications

J. Chu, L. Brooks, and H.-S. Lee, “A Zero-Crossing Based 12b 100MS/s Pipelined ADC with Decision Boundary Gap Estimation Calibration,” Symposium on VLSI Circuits, Honolulu, HI, June 2010.

A. Chow and H.-S. Lee, “Offset Cancellation for Zero Crossing Based Circuits,” IEEE ISCAS, Paris, France, June 2010.

P. Lajevardi, A. Chandrakasan, and H.-S. Lee, “Zero-Crossing Detector Based Reconfigurable Analog System,” A-SSCC 2010, Beijing, China, November 2011

H.-S. Lee, “MOS A/D Converters: Development of Capacitor Array ADCs and Digital Self-Calibration,” ISSCC Special Evenings Session, San Francisco, CA, Feb. 2011

A. Chang, H.-S. Lee and D. Boning, “Redundancy in SAR ADCs,” GLSVLSI ’11, Lausanne, Switzerland, May 2011

Fully Electronic, Wearable Transcranial Doppler Ultrasonograph System

• Authors: S. Pietrangelo, C. G. Sodini, H.-S. Lee
• Sponsorship: Lincoln Laboratory Fellowship, CICS

Intracranial pressure (ICP) is a key factor in monitoring a patient’s cerebrovascular state.  However, current ICP measurement modalities are highly invasive, relying on surgical penetration of the skull.  Recent developments in model-based physiology allow ICP to be estimated using arterial blood pressure and cerebral blood flow velocity (CBFV) measurements ^[1] .  CBFV can be obtained non-invasively using transcranial Doppler (TCD) ultrasonography, but requires bulky capital equipment and an expert operator to manually focus the ultrasound beam on a particular intracranial blood vessel.  Therefore, TCD measurements of CBFV are currently restricted to clinical environments in which such technology and expertise are available (typically neurocritical care units).

This project seeks to develop a low-power, miniaturized TCD ultrasonography system for measuring CBFV in the middle cerebral artery (MCA) in support of continuous monitoring of ICP.  The MCA is typically about 3 mm in diameter and is insonated through the temporal bony window at a distance of 40 to 60 mm from the ultrasonic transducer array.  These anatomic considerations place significant constraints on the focal length and spatial resolution requirements of the transducer array.  Adjusting the transmit amplitude and phase of each element in the 2D transducer array via a digital beamformer and high voltage (HV) pulser achieves electronic beam steering in three spatial dimensions.  Figure 1 shows relative acoustic power density for a 15° off-axis focus using a 2D transducer array with electronic beam steering.

Development of a beam steering algorithm will allow for autonomous location of the MCA, eliminating the need for a skilled operator. TCD ultrasonography focusing is further complicated by the highly non-homogenous acoustic propagating medium (i.e., presence of high-density cranium).   This issue can be mitigated, however, using calibration methods ^[2] . An HV multiplexer (MUX) is utilized so that a single transmit/receive (T/R) channel can connect to multiple transducer elements and thus greatly reduce the necessary electronics and power requirements.  This system architecture, as illustrated in Figure 2, will allow for a self-contained system for continuous CBFV measurement in a low-power and wearable form-factor.



Figure 1: Relative acoustic power density (in XZ plane) demonstrating beam steering for a 15° off-axis focus.



Figure 2: Pulsed wave ultrasonography block diagram.




1. F. M. Kashif, T. Heldt, and G. C. Verghese. “Model-based estimation of intracranial pressure and cerebrovascular autoregulation,” Computers in Cardiology, vol. 35, pp. 369-372, Sep. 2008. [↩]
2. G.T. Clement and K. Hynynen, “A non-invasive method for focusing ultrasound through the human skull,” Physics in Medicine and Biology, vol. 47, pp. 1219-1236, Apr. 2002. [↩]

Analog Front-end Design for Portable Ultrasound Systems

• Authors: K. Chen, S. Lee, B. Lam, H.-S. Lee, A. P. Chandrakasan, C. G. Sodini
• Sponsorship: SRC/FCRP C2S2

The Capacitive Micromachined Ultrasound Transducer (CMUT) is an alternative to traditional piezoelectric transducers. The CMUT technology provides an opportunity for highly integrated ultrasound-imaging system solutions because of its CMOS compatibility, ease of large array fabrication, and improved bandwidth and sensitivity performance ^[1] .

This project aims to provide a highly flexible platform for 3D ultrasound imaging. Figure 1 presents the system architecture. The CMUT device is flip-chip bonded to the supporting electronic circuits, which eliminates the cables that are usually required by traditional systems between the piezoelectric transducers and circuits. As a result, the channel count of the imaging system is increased and the capacitive loading due to cables is greatly reduced.

The first prototype chip of the transmitter and receiver analog front-end for a 1D CMUT array is fabricated and is under testing. The block diagram of the implemented chip is shown in Figure 2. It contains four channels of independent transmitters and receiver chains. External control can be implemented for beamforming and Time-Gain Compensation (TGC). In each channel, the transmitter generates high voltage electric pulses to drive the CMUT device. A 3-level pulse shaping transmitter is designed to increase the transmitted signal power within the transducer bandwidth. The design uses MOS high voltage transistors for a pulse magnitude as large as 32 Vpp. The pulse frequency is programmable between 1~10 MHz and the pulse duration is programmable between about 0.5~20 us.

On the receiver side, a Low Noise Amplifier (LNA) implemented with a trans-impedance amplifier interfaces to the CMUT. The LNA is optimized for noise, power, and bandwidth trade-offs. The LNA can also be switched from “on” and “off” within 5 us. This switching saves system power when LNA is not needed. A Variable Gain Amplifier (VGA) follows the LNA to realize the Time-Gain Compensation function. Instead of a linear TGC profile, this VGA implements the TGC in a low power way, with discrete gain steps to compensate signal attenuation with coarse resolution. The VGA consumes 300 uA, and the gain setting can be changed in 6 dB per step with a tunable range of about 54 dB.

The prototyped chip is 3 mm X 3 mm in size. The simulated performance shows that each receive channel consumes 18.1 mW in normal mode and 1.7 mW in sleep mode. The programmable Rx gain range is from 152 dB to 99 dB at 3 MHz, with gain steps of 6 dB per step. The Rx Bandwidth is 6.0 MHz and the Rx Noise Figure is 11.3 dB within the signal bandwidth. The Tx pulsing energy efficiency is 38.2 nJ / pulse for an assumed 60 pF load from one CMUT element.



Figure 1: The architecture of a 3D ultrasound imaging system with CMUT devices.



Figure 2: The block diagram of the first prototype ultrasound analog front-end chip.




1. O. Oralkan, “Acoustical imaging using capacitive micromachined ultrasonic transducer arrays: Devices, circuits, and systems,” Ph.D. dissertation, Stanford, Palo Alto, 2004. [↩]

Continuous-Time Delta-Sigma Analog-to-Digital Converters for Application to a Multiple-Input Multiple-Output System

• Authors: D. Yoon, H.-S. Lee
• Sponsorship: MediaTek Wireless, Inc.

Wireless communication technology is rapidly advancing, and new wireless applications are continuously developed. Figure 1 shows each application and the required dynamic range ^[1] . The new wireless applications demand wideband and high-resolution data converters. In this situation, delta-sigma (ΔΣ ) analog-to-digital converters (ADCs) are suitable, because they provide low-power and high-resolution characteristics. These ΔΣ  ADCs can be implemented in either a discrete-time (DT) or a continuous-time (CT) structure. Since DT ΔΣ ADCs, based on switched capacitors, require op amp settling within each half clock period, the gain-bandwidth requirement for the op amp is rather high. The CT ΔΣ ADCs require much lower gain-bandwidth. Thus, it is possible for CT ΔΣ ADCs to function at higher sampling frequency and achieve wide bandwidth compared to DT ΔΣ ADCs. In addition, since the CT ΔΣ  ADCs are more power-efficient and have an inherent anti-aliasing property, they are more suitable for the demanding new wireless applications.

This project focuses on the design of CT ΔΣ ADCs, and specifically for the application in Multiple-Input Multiple-Output wireless receivers. For this application, each CT ΔΣ ADC in a channel must provide wide bandwidth and high dynamic range at low power consumption. Recent state-of-art CT ΔΣ ADCs did not achieve wide enough bandwidth or high enough dynamic range for such application ^{[2] [3]} . We are investigating new types of noise-coupled time-interleaved ΔΣ ADCs ^[1] for MIMO systems. Figure 2 shows the overall structure of noise-coupled time-interleaved ADCs. We are currently investigating techniques that exploit correlation between channels in multi-channel noise coupled system.



Figure 1: Dynamic range and bandwidth requirements of ADCs in wireless applications.



Figure 2: The overall structure of noise-coupled time-interleaved ΔƩ ADCs.




1. K. Lee, J. Chae, M. Aniya, K. Hamashita, K. Takasuka, S. Takeuchi, and G.C. Temes l., “A Noise-Coupled Time-Interleaved Delta-Sigma ADC With 4.2 MHz Bandwidth, 98 dB THD, and 79 dB SNDR,” IEEE J. Solid-State Circuits, vol. 43, no. 12, pp. 2601-2612, Dec. 2008. [↩] [↩]
2. M. Bolatkale, L.J. Breems, R. Rutten, and K.A.A. Makinwa, “A 4GHz CT ΔΣ ADC with 70dB DR and −74dBFS THD in 125MHz BW,” ISSCC Dig. Tech. Papers, pp. 470-472, Feb. 2011. [↩]
3. G. Mitteregger, C. Ebner, S. Mechnig, T. Blon, C. Holuigue, E. Romani, A. Melodia, and V. Melini, , “A 14b 20mW 640MHz CMOS CT ΔΣ ADC with 20MHz Signal Bandwidth and 12b ENOB,” ISSCC Dig. Tech. Papers, pp. 131-140, Feb. 2006. [↩]

A High-accuracy, Zero-crossing-based Pipeline ADC

• Authors: M. Markova, P. Holloway, H.-S. Lee
• Sponsorship: CICS

Technology scaling poses challenges in designing analog circuits because of the decrease in intrinsic gain and reduced swing. An alternative to using high-gain amplifiers in the implementation of switched capacitor circuits has been proposed ^[1] that replaces the amplifier with a current source and a comparator. The new comparator-based switch capacitor (CBSC) and zero-crossing-based circuit (ZCBC) techniques have been implemented in two pipelined ADC architectures at 10 MHz and 200 MHz and 10-bit and 8-bit accuracy, respectively ^{[1] [2]} .

The purpose of this project is to explore the use of the ZCBC technique for very-high-precision AD converters. The goal of the project is a 100 MHz, 14-bit pipelined ADC. First, we are investigating dual-phase hybrid ZCBC operation to improve the power-linearity tradeoff of the A/D conversion ^[3] and to improve the power supply rejection. The first phase approximates the final output value, while the second phase allows the output to settle to its accurate value. Since the output is allowed to settle in the second phase, the currents through capacitors decay, permitting higher accuracy and power-supply rejection compared with standard ZCBCs.  We are also developing linearization techniques for the ramp waveforms. Linear ramp waveforms require less correction in the second phase for given linearity, thus allowing faster operation. Innovative techniques for improving linearity beyond using a cascoded current source are explored; these techniques include output pre-sampling and bi-directional output operation. In addition, overshoot reduction calibration is implemented to improve the linearity requirements of the final phase. Digital self- calibration will be explored to reduce the residual constant offset. The ADC was implemented in a 65-nm 1-V process, and its operation is currently being evaluated.

1. T. Sepke, J. K. Fiorenza, C. G. Sodini, P. Holloway, and H.-S. Lee, “Comparator-based switched capacitor circuits for scaled CMOS technologies,” IEEE International Solid State Circuits Conference Digest of Technical Papers, Feb. 2006, pp. 220-221. [↩] [↩]
2. L. Brooks and H.-S. Lee, “A zero-crossing based 8b 200MS/s pipelined ADC,” IEEE International Solid State Circuits Conference Digest of Technical Papers, Feb. 2007, pp. 460-461. [↩]
3. J. K. Fiorenza, “A comparator-based switched –capacitor pipelined analog-to-digital converter,” Ph.D. thesis, Massachusetts Institute of Technology, Cambridge, 2007. [↩]

Front-end Design for Portable Ultrasound Systems

• Authors: S. Lee, K. Chen, B. Lam, C. G. Sodini, A. P. Chandrakasan, H.-S. Lee
• Sponsorship: CICS, SRC/FCRP C2S2



Figure 1

Most current ultrasound imaging systems use piezoelectric materials for the ultrasound transducer. The recent development of micro-electromechanical systems (MEMS) allowed fabrication of capacitive micromachined ultrasound transducers (CMUTs).  A CMUT is a micromachined capacitor whose value changes according to the DC bias voltage or external pressure due to the physical deformation of the top plate by electrostatic force or external pressure. The major advantages of this transducer technology are the potential for integration with supporting electronic circuits, ease of fabrication, higher resolution due to small transducer size, and improved bandwidth and sensitivity ^[1] .

This project focuses on the front-end design of portable ultrasound systems using CMUTs. Figure 1 presents a conceptual block diagram of the system. Implementing an ADC at each channel input makes possible digital beam-forming in the receive (Rx) path, which enhances ultrasound image quality. To implement as many ADCs as the number of transducer channels, each ADC must consume as little power as possible, and each should be implemented in a small area. Considering the required performance, a zero-crossing-based (ZCB) pipelined ADC is a suitable architecture ^[2] .  For the first part of this project, a 50-MHz 12-bit ZCB pipelined ADC is designed. The highly digital implementation characteristic of the zero-crossing detection technique enables energy-efficient operation and voltage scaling. Supply voltage scaling based on the required sampling frequency and resolution provides constant energy efficiency over a wide range of sampling frequencies and resolutions.

Recently, a few 2D imaging systems using CMUT as ultrasound transducers have been reported, but they do not use real-time imaging ^[1] . The digital image processing block will be considered in the system level for real-time imaging.  After completing the 2D ultrasound image system using a 1D transducer, we will examine the feasibility of the 3D ultrasound image system using 2D transducers.

1. O. Oralkan, “Acoustical imaging using capacitive micromachined ultrasonic transducer arrays: Devices, circuits, and systems,” Ph.D. thesis, Stanford University, Palo Alto, CA, 2004. [↩] [↩]
2. L. Brooks and H.-S. Lee, “A zero-crossing-based 8b 200MS/s pipelined ADC,” IEEE International Solid-State Circuits Conference, 2007. Digest of Technical Papers, pp. 460-615. [↩]

Time-interleaved A/D Converters

• Authors: D. P. Kumar, H.-S. Lee
• Sponsorship: Qualcomm, MASDAR

There is an ever-increasing demand for high resolution and high accuracy in A/D converters in communication systems. In order to raise the sampling rates to the GHz range in a power efficient manner, time-interleaving is an essential technique. The biggest problem in time-interleaved ADCs is the sampling clock skew between different channels. This problem becomes especially acute when high resolution and high sampling rate are required simultaneously.

There are a few sources of sampling skew between channels. Mismatches in the sampling clock path and logic delays are the most obvious. Input signal routing mismatch and the RC mismatch of the input sampling circuit also cause sampling skew. No prior study has quantified these sources of timing skew to determine the main cause of the sampling skew. In this research, we will first build test chips specifically designed to determine the degree of sampling skew mismatch that the various possible sources contribute.

The sampling skew can be mitigated by various calibration techniques. Previous calibration techniques employ either analog timing adjustment or digital calibration of output data. The timing adjustment requires adjustable delay and increases sampling jitter, which cannot be compensated by calibration. The digital calibration of output data requires complex interpolation. In this research, we will develop a much simpler calibration algorithm for sampling skew based on consecutive sampling. The consecutive sampling allows a very simple linear interpolation, and the impact on noise or power consumption in the analog circuit is negligible. Since the calibration algorithm is simple, the power consumption in digital circuits will be low. We will implement a high-speed time-interleaved ADC to demonstrate the new calibration.

Time-interleaved Zero-crossing Based ADC

• Authors: J. Chu, H.-S. Lee
• Sponsorship: SRC/FCRP C2S2, SRC/FCRP C2S2

In zero-crossing based circuits (ZCBC), op-amps in pipelined ADCs are replaced with zero-crossing detectors (ZCDs). The closed-loop feedback provided by the op-amp is replaced with a semi-open-loop switched-capacitor structure ^{[1] [2] [3] [4]} .  The power efficiency of ZCBC has been demonstrated in various pipelined ADC designs ^{[1] [2] [3] [4]} .

Time-interleaving can be applied to most ADC architectures to increase the overall sampling rate. The combined ADC’s accuracy and dynamic performance is limited by the matching between the different ADC channels. Mismatch in the offset, gain, and sampling time skew of the ADC channels degrade the combined signal to noise and distortion ratio (SNDR). In this work, we implemented a time-interleaved zero-crossing based (ZCB) time-interleaved ADC. The core pipelined ADC design is similar to the work presented in ^[4] . The interchannel interference through the reference voltage is reduced by the reference precharging scheme. The timing skew between channels is calibrated by foreground calibration.

In this time-interleaved ADC, the gain mismatch and the offset mismatch between the ADCs are measured and removed digitally. The offset is measured with a zero input and removed digitally. The gain error is measured by measuring the peak to peak values when the ADC is driven with a full-scale sine wave. The ADC code of each channel is digitally scaled to remove the gain error. The timing skew is also measured and corrected using variable delay elements. In the measurement results, the ADC achieves 8.7 ENOB and 61 dB SFDR with a 211-MHz input signal while sampling at 450 MS/s. The ADC uses a 1.2-V supply and consumes 34 mW. This result corresponds to a figure of merit of 182 fJ/step.

1. J. K. Fiorenza, T. Sepke, P. Holloway, C. G. Sodini, and H.-S. Lee, “Comparator based switched capacitor circuits for scaled CMOS Technologies,” IEEE Journal of Solid-State Circuits, vol. 41, no. 12, Dec. 2006, pp. 2658 – 2668. [↩] [↩]
2. L. Brooks and H.-S. Lee, “A zero-crossing based 8b 200MS/s  pipelined ADC,” IEEE ISSCC Dig. Tech. Papers, Feb. 2007, pp. 460-461. [↩] [↩]
3. L. Brooks and H.-S. Lee, “A 12b 50MS/s fully differential zero-crossing based ADC without CMFB,” ISSCC Dig. Tech. Papers, Feb. 2009, pp. 166-167. [↩] [↩]
4. J. Chu, L. Brooks, and H.-S. Lee, “A zero-crossing based 12b 100MS/s pipelined ADCs with decision boundary gap estimation calibration,” IEEE VLSI Circuits Dig. Tech Papers, June 2010, pp. 237-238. [↩] [↩] [↩]

A Low-power SAR ADC with Redundancy

• Authors: A. H. Chang, H.-S. Lee, D. S. Boning
• Sponsorship: Masdar Institute of Science and Technology

Technology scaling has enabled low-power operations in digital integrated circuits.  Therefore, the trend to move analog-to-digital operations upstream to allow more signal-processing to shift from the analog domain to the digital domain is inevitable. As most real world signals remain analog, the design of high-performance and low-power analog-digital converters (ADCs) plays a key role to the success of future integrated system design. In this research, we focus on designing (1) robust, (2) low-power, and (3) high-performance time-interleaved successive-approximation-registers (SAR) ADCs. The SAR architecture is adopted because of its good digital compatibility and high energy-efficiency while achieving high sampling rates.

The robustness of SAR ADCs is achieved by analyzing the effectiveness of redundancy (digital error correction) ^{[1] [2]} in improving sampling rates and its immunity from incomplete bit settling errors. Analysis shows that the redundancy algorithm does not help improve sampling rate in all SAR ADC designs; instead, the maximum sampling rate depends on the settling time constant (τ) and the relative magnitude of the ADC delay components ^[3] . As shown in Figure 1, in order to benefit from the redundancy algorithm, τ has to be more than 50 ps.

The low-power operation is achieved by combining the merged capacitor switching algorithm ^[4] and split capacitive array ^[5] . The merged capacitor switching algorithm suffers from its sensitivity to the parasitic capacitance on the outputs of the capacitive DAC. The split capacitive array suffers from a 4x loss in signal power to keep voltage below the supply rail on the sub-DAC and the mismatch problem between the fractional bridge capacitor to other capacitors in the DAC. Our design researches and resolves both issues. Our design also incorporated asynchronous on-chip pulse generator to avoid synchronous high power clock distribution circuit on-chip. The overall SAR ADCs architecture is depicted in Figure 2.



Figure 1: Speed improvement from adopting redundancy ^[2] .



Figure 2: Overall SAR ADCs architectures.




1. F. Futtner, “A 1.2V 10b 20MSample/s non-binary successive approximation ADC in 0.13μm CMOS,” in IEEE International of Solid-State Circuit Conference Digest of Technical Papers, pp. 136-137, 2002. [↩]
2. T. Ogawa, H. Kobayashi, M. Hotta, Y. Takahashi, H. San, and N. Takai, “SAR ADC algorithm with redundancy,” in IEEE APCCAS, pp. 268-271, Nov. 2008. [↩] [↩]
3. A. H. Chang, H.-S. Lee, and D. S. Boning, “Redundancy in SAR ADCs,” in Great Lakes Symposium on VLSI, May 2011. [↩]
4. V. Hariprasath, J. Guerber, S.-H. Lee, and U.-K. Moon, “Merged capacitor switching based SAR ADC with highest switching energy-efficiency,” Electronics Letters, vol. 46, pp. 620-621, April 2010. [↩]
5. Y. Chen, X. Zhu, H. Tamura, M. Kibune, Y. Tomita, T. Hamada, M. Yoshioka, K. Ishikawa, T. Takayama, J. Ogawa, S. Tsukamoto, and T. Kuroda, “Split capacitor DAC mismatch calibration in successive approximation ADC,” in IEEE Custom Integrated Circuits Conference, pp. 279 –282, 2009. [↩]