MTL Annual Research Report 2011

There is an ever-increasing demand for high resolution and high accuracy in A/D converters in communication systems. In order to raise the sampling rates to the GHz range in a power efficient manner, time-interleaving is an essential technique. The biggest problem in time-interleaved ADCs is the sampling clock skew between different channels. This problem becomes especially acute when high resolution and high sampling rate are required simultaneously.

There are a few sources of sampling skew between channels. Mismatches in the sampling clock path and logic delays are the most obvious. Input signal routing mismatch and the RC mismatch of the input sampling circuit also cause sampling skew. No prior study has quantified these sources of timing skew to determine the main cause of the sampling skew. In this research, we will first build test chips specifically designed to determine the degree of sampling skew mismatch that the various possible sources contribute.

The sampling skew can be mitigated by various calibration techniques. Previous calibration techniques employ either analog timing adjustment or digital calibration of output data. The timing adjustment requires adjustable delay and increases sampling jitter, which cannot be compensated by calibration. The digital calibration of output data requires complex interpolation. In this research, we will develop a much simpler calibration algorithm for sampling skew based on consecutive sampling. The consecutive sampling allows a very simple linear interpolation, and the impact on noise or power consumption in the analog circuit is negligible. Since the calibration algorithm is simple, the power consumption in digital circuits will be low. We will implement a high-speed time-interleaved ADC to demonstrate the new calibration.