All entries for Eugene Fitzgerald

• Print This Page
• Download as PDF

Eugene Fitzgerald

• Title: Merton C. Flemings-Singapore MIT Alliance Professor of Materials Engineering
• Department: Department of Materials Science and Engineering
• URL: http://sauvignon.mit.edu

Graduate Students

• Yu Bai, Res. Asst., DMSE
• Steve Boles, Res. Asst., DMSE
• Chengwei Chen, Res. Asst., DMSE
• Adam Jandl, Res. Asst., DMSE
• Li Yang, Res. Asst., DMSE
• Nan Yang, Res. Asst., DMSE
• Prithu Sharma, Res. Asst., DMSE

Research Scientist

• Dr. Mayank Bulsara

Support Staff

• Gabrielle Joseph

Publications

Self-cleaning and surface recovery with arsine pretreatment in ex situ atomic-layer-deposition of Al₂O₃ on GaAs, Cheng-Wei Cheng; Hennessy, J.; Antoniadis, D.; Fitzgerald, E.A. Applied Physics Letters,  v 95, n 8, p 082106 (3 pp.),  24 Aug. 2009.

Thermal considerations for advanced SOI substrates designed for III-V/Si heterointegration; Yang, N; Bulsara, M.T.; Fitzgerald, E.A.; Liu, W.K.; Lubyshev, D.; Fastenau, J.M.; Wu, Y.; Urteaga, M.; Ha, W.; Bergman, J.; Brar, B.; Drazekd, C.; Daval, N.; Benaissa, L.; Augendre, E.; Hoke, W.E.; LaRoche, J.R.; Herrick, K.J.; Kazior, T.E. 2009 IEEE International SOI Conference, p 2 pp.,  2009.

Arrayed Si/SiGe nanowire and heterostructure formations via au-assisted wet chemical etching method; Wang, X. ; Pey, K.L.; Choi, W.K.; Ho, C.K.F.; Fitzgerald, E.; Antoniadis, D. Electrochemical and Solid-State Letters, v 12, n 5, p 37-40,  May 2009.

Linearly polarized light emission from InGaN light emitting diode with subwavelength metallic nanograting; Liang Zhang ; Jing Hua Teng; Soo Jin Chua; Fitzgerald, E.A. Applied Physics Letters,  v 95, n 26, p 261110 (3).

Growth of highly tensile-strained Ge on relaxed In_xGa_1-xAs by metal-organic chemical vapor deposition; Yu Bai ; Lee, K.E.; Chengwei Cheng; Lee, M.L.; Fitzgerald, E.A. Journal of Applied Physics,  v 104, n 8, p 084518 (9 pp.),  15 Oct. 2008.

Annihilation of threading dislocations in strain relaxed nano-porous GaN template for high quality GaN growth; Hartono, H. Soh, C.B.; Chua, S.J.; Fitzgerald, E.A. Physica Status Solidi C,  v 4, n 7, p 2572-5,  June 2007.

In situ metal-organic chemical vapor deposition atomic-layer deposition of aluminum oxide on GaAs using trimethyaluminum and isopropanol precursors; Cheng, C.-W. ; Fitzgerald, E.A. Applied Physics Letters,  v 93, n 3, p 031902-1-3,  21 July 2008

MBE growth of InP-HBT structures on Ge-on-insulator/Si substrates by MBE; Lubyshev, D. ; Fastenau, J.M.; Wu, Y.; Liu, W.K.; Urteaga, M.; Ha, W.; Bergman, J.; Brar, B.; Bulsara, M.T.; Fitzgerald, E.A.; Hoke, W.E.; LaRoche, J.R.; Herrick, K.J.; Kazior, T.E. 2008 IEEE 20th International Conference on Indium Phosphide & Related Materials (IPRM), p 3 pp.,  2008.

Alternative slip system activation in lattice-mismatched InP/InGaAs interfaces; Quitoriano, N.J. ; Fitzgerald, E.A. Journal of Applied Physics,  v 101, n 7, p 73509-1-10,  1 April 2007.

Monolithic III-V/Si integration; Fitzgerald, E.A. ; Bulsara, M.T.; Bai, Y.; Cheng, C.; Liu, W.K.; Lubyshev, D.; Fastenau, J.M.; Wu, Y.; Urtega, M.; Ha, W.; Bergman, J.; Brar, B.; Drazek, C.; Daval, N.; Letertre, F.; Hoke, W.E.; LaRoche, J.R.; Herrick, K.J.; Kazior, T.E. 2008 9th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT), p 4 pp.,  2008.

Monolithic CMOS-compatible AlGaInP visible LED arrays on silicon on lattice-engineered substrates (SOLES); Chilukuri, K.; Mori, M.J.; Dohrman, C.L.; Fitzgerald, E.A. Semiconductor Science and Technology,  v 22, n 2, p 29-34,  Feb. 2007.

Fabrication of silicon on lattice-engineered substrate (SOLES) as a platform for monolithic integration of CMOS and optoelectronic devices; Dohrman, C.L. ; Chilukuri, K.; Isaacson, D.M.; Lee, M.L.; Fitzgerald, E.A. Materials Science & Engineering B (Solid-State Materials for Advanced Technology),  v 135, n 3, p 235-7,  15 Dec. 2006.

Strained and relaxed SiGe for high-mobility MOSFETs; Lee, M.L. ; Antoniadis, D.A.; Fitzgerald, E.A. 2006 International SiGe Technology and Device Meeting (IEEE Cat. No. 06EX1419), p 158-9,  2006.

Experiment and Simulation on Channel Mobility of In_0.53Ga_0.47As Quantum-well MOSFET Structures

• Authors: L. Yang, C. Cheng, M. T. Bulsara, E. A. Fitzgerald
• Sponsorship: SRC/FCRP MSD

This paper discusses a way to optimize the In_0.53Ga_0.47As quantum-well MOSFET structures from the prospective of channel mobility. We experimentally demonstrated that the barrier thickness and interfacial defect density are two key factors determining the channel mobility, while the effect of the oxide charge is negligible. The mobility model consisting of phonon scattering and coulomb scattering was applied to fit the experimental data. According to the model, for quantum-well MOSFET structures with in-situ ALD Al₂O₃, the mobility is dominated by coulomb scattering for the thin barrier case (<5 nm) and dominated by phonon scattering for the thick barrier case (>5 nm). At a barrier thickness of 4 nm, compared to a structure with in-situ ALD Al₂O₃ with the mobility of 6807 cm²/Vs, which corresponds to an interfacial charged defect density of 1.1×10¹³ cm^-2, the structure with in-situ CVD Al₂O₃ showed higher mobility (8883 cm²/Vs), which corresponds to a lower charged defect density (5×10¹² cm^-2).



Figure 1: Channel electron mobility versus the thickness of InGaAs/InAlAs barrier. The blue diamond symbols indicate the measured mobility. The magenta and red dots indicate the mobility limited by coulomb scattering and phonon scattering, respectively, and the black “+” symbols indicate the simulated final mobility.



Figure 2: Channel electron mobility versus the charged defect density. The blue diamond symbol and the green square symbol indicate the measured mobility for structure with CVD Al₂O₃/InGaAs interface and ALD Al₂O₃/InGaAs interface, respectively. The magenta and red dots indicate the mobility limited by coulomb scattering and phonon scattering, respectively, and the black “+” symbols indicate the simulated final mobility.




High-efficiency, Low-cost Photovoltaics Using III-V on Silicon Tandem Cells

• Authors: P. Sharma, M. T. Bulsara, E. A. Fitzgerald
• Sponsorship: Singapore-MIT Alliance



Figure 1: Cross-sectional <220> bright field TEM of GaAsyP1-y on (a) Si_0.5Ge_0.5 and (b) Si_0.4Ge_0.6 virtual substrates on 6° offcut towards the nearest {111} plane Si (001) substrate.

Photovoltaics and sustainability have received a lot of attention lately. We seek a tandem photovoltaic device using silicon as both the substrate and lower cell and GaAsP as the upper cell. The ideal band gaps for this two-cell tandem structure with silicon at 1.1eV and GaAsP at 1.75 eV allows access to the highest efficiency possible for a two-cell tandem, 36.5%. The lattice mismatch between GaP and Si is 0.37%; therefore, these two materials constitute a nearly ideal combination for the integration of Si and III–V semiconductor-based technologies. But defect-free heteroepitaxy of GaP on Si has nevertheless been a major challenge.

One can envision a process in which a Si_1-xGe_x graded buffer is grown on a Si wafer to extend the lattice parameter part of the way to GaAs, at which point a lattice-matched GaAs_yP_1-y is grown on the Si_1-xGe_x surface, followed by tensile grading of the GaAs_yP_1-y until GaP is reached. Identifying the composition where the transition can be made from Si_1-xGe_x to GaAs_yP_1-y depending on the application is an integral objective of this study. This study will provide the flexibility to engineer the lattice constants from Si to Ge and GaP to GaAs while maintaining low threading dislocation density (TDD) and surface morphology suitable for device processing. In this study the successful growth of high-quality lattice-matched GaAs_yP_1-y on Si_0.5Ge_0.5, Si_0.4Ge_0.6, and Si_0.3Ge_0.7 virtual substrates has been achieved. Various characterization techniques clearly reveal a high quality crystalline interface (Figure 1) between Si_1-xGe_x and GaAs_yP_1-y with low TDD suitable for device processing and no rampant dislocation nucleation, anti-phase boundaries, stacking faults, or other crystalline defects.  Further work will explore the temperature window for the epitaxial growth of GaAs_yP_1-y on Si_1-xGe_x with higher Si content, as the end goal is to get a defect-free GaP film on Si substrate.

Platform for Monolithic Integration of III-V Devices with Si CMOS

• Authors: N. Y. Pacella, M. T. Bulsara, E. A. Fitzgerald
• Sponsorship: DARPA COSMOS Program, Raytheon



Figure 1: Cross-sectional TEM image of the SOLES structure.

Monolithic integration of III-V devices with Si CMOS technology allows us to combine the unique capabilities of III-V devices with the economies of scale and established infrastructure of Si CMOS to create advanced circuits with new functionalities.  We have developed the silicon-on-lattice-engineered-silicon (SOLES) substrate platform in order at accomplish this goal ^{[1] [2] [3] [4]} .  The SOLES structure is a silicon substrate with an embedded III-V template.  One version of it is illustrated in Figure 1.  First, Si CMOS devices are fabricated on the top silicon-on-insulator layer due to their high thermal budget requirements.  Once the Si devices are in place, the III-V template can be accessed by etching windows in the top Si and oxide.  III-V device structures can then be grown from the III-V template to be coplanar with the CMOS devices.  If these III-V devices are encapsulated with Si, CMOS silicide contacts can be made to both the Si and III-V in parallel.

InP metamorphic heterojunction bipolar transistors (mHBTs) and Si CMOS devices have been successfully integrated on SOLES wafers, although with traditional III-V and CMOS contact technology ^[5] .  We are now working to establish a CMOS metallization scheme for III-V devices based on silicide technology.  We are also developing improved versions of the SOLES structure, with direct incorporation of high quality III-V template layers.

1. C. L. Dohrman, K. Chilukuri, D. M. Isaacson, M. L. Lee, and E. A. Fitzgerald, “Fabrication of silicon on lattice-engineered substrate (SOLES) as a platform for monolithic integration of CMOS and optoelectronic devices,” Materials Science and Engineering B: Solid-State Materials for Advanced Technology, vol. 135, no. 3, pp. 235-237, Dec. 2006. [↩]
2. F. Letertre, “Formation of III-V semiconductor engineered substrates using Smart CutTM layer transfer technology,” in Mater. Res. Soc. Symp. Proc. 2008, vol. 1068, pp. 1068-C01-01. [↩]
3. K. Chilukuri, M. J. Mori, C. L. Dohrman, and E. A. Fitzgerald, “Monolithic CMOS-compatible AlGaInP visible LED arrays on silicon on lattice-engineered substrates (SOLES),” Semiconductor Science and Technology, vol. 22, pp. 29-34, 2007. [↩]
4. N. Yang, M. T. Bulsara, E. A. Fitzgerald, W. K. Liu, D. Lubyshev, J.M. Fastenau, Y. Wu, M. Urteaga, W. Ha, J. Bergman, B. Brar, C. Drazek, N. Daval, L. Benaissa, E. Augendree W. E. Hoke, J. R. LaRoche, K. J. Herrick, and T. E. Kazior, “Thermal considerations for advanced SOI substrates designed for III-V/Si heterointegration,” in 2009 IEEE International SOI Conference, pp. 121-122. [↩]
5. W. K. Liu, D. Lubyshev, J. M. Fastenau, Y. Wu, M. T. Bulsara, E. A. Fitzgerald, M. Urteaga, W.  Ha, J. Bergman, B. Brar, W. E. Hoke, J. R. LaRoche, K. J. Herrick, T. E. Kazior, D. Clark, D. Smith, R. F. Thompson, C. Drazek, and N. Daval, “Monolithic integration of InP-based transistors on Si substrates using MBE,” J. Crystal Growth, vol. 311, no. 7, pp. 1979–1983, Mar. 2009. [↩]

III-V and IV Semiconductors for Thermoelectric and Thermophotovoltaic Applications

• Authors: A. C. Jandl, M. Bulsara, E. A. Fitzgerald
• Sponsorship: Solid-State Solar-Thermal Energy Conversion Center

We are developing materials for thermoelectric and thermophotovoltaics applications.  Our objective is to develop III-V and/or IV superlattices with low thermal conductivity and high electrical conductivity to maximize the thermoelectric figure of merit.  Additionally, it may be possible to increase the Seebeck coefficient in these materials by introducing a narrow but large peak in the density of states near the Fermi energy.  For our thermophotovoltaics research, we are investigating graded buffers of InAsP as a platform for the growth of low defect density InAsP, InGaAs, and GaAsSb tandem photovoltaic cells with band gap energies in the range of 0.6 eV to 0.8 eV.

Through our collaborations we have designed and created GaAs/AlAs superlattices (SL) to determine the method of phonon transport in semiconducting superlattices.  Measurements by our collaborators have revealed that thermal transport may not be diffusive and further work is being done to investigate this transport.  GaAs/Ge structures have also been grown but lack planar interfaces due to surface kinetics during growth.  Future experiments will explore the growth of GaAs and Ge structures and determine the thermal and electrical transport properties in these systems.  Figure 1 is a dark field cross-section TEM image of this sample.

Our work on thermophotovoltaics is two-pronged, with one focusing on minimizing threading dislocation densities (TDD) introduced by InAsP graded buffers and the other focusing on the growth and doping of InAsP and InGaAs pn-junctions with band gap energies in the range of 0.6 eV to 0.8 eV.  Our work on InAsP graded buffers has focused on determining the relationship between the strain accumulation rate in the buffer and the resulting TDD in the active regions.  The pn-junctions shown in Figure 2 targeted two compositions of InGaAs and one of InAsP to achieve the desired band gap energies.



Figure 1: Cross-sectional bright field <220> TEM images of InGaAs and InAsP pn-junctions. The band gap energy of the top- most layer of each structure is (a) 0.6 eV, (b) 0.7 eV, and (c) 0.8 eV.



Figure 2: Cross-section dark field TEM image of GaAs/Ge multilayer on GaAs (001) 6° offcut towards the nearest {111} plane. The bright regions in the film are GaAs, and the dark regions are Ge.




Fabrication of GaAs-on-Insulator via Low-temperature Wafer Bonding and Sacrificial Etching of Ge by XeF2

• Authors: Y. Bai, E. A. Fitzgerald
• Sponsorship: Singapore-MIT Alliance

Front-end integration of III-V compound semiconductor devices with Si metal-oxide-semiconductor (MOS) technology requires the development of commercially viable engineered substrates ^{[1] [2]} . The fabrication of engineered substrates currently utilizes technologies such as epitaxy, wafer bonding, and layer exfoliation.  We report on the development of GaAs-on-insulator (GaAsOI) structures without the use of Smartcut^TM technology. GaAs/Ge/GaAs epitaxial stacks containing an embedded Ge sacrificial release layer were grown with metal-organic chemical vapor deposition (MOCVD) and exhibit both a low defect density as well as surface properties suitable for wafer bonding ^[3] .  A room-temperature oxide-oxide bonding process was developed to enable the integration of substrates with a large difference in their coefficients of thermal expansion. The release of the donor substrate and transfer of the GaAs layer onto the handle substrate were realized through room-temperature, gas-phase lateral etching of an embedded Ge sacrificial layer by xenon difluoride (XeF₂). Figure 1 schematically shows our fabrication process. This GaAsOI fabrication process is shown to be successful on a small scale. Figure 2 shows a cross-sectional TEM image of the final GaAsOI/Si structure fabricated with this process. Implementation of this process for fabricating large-area GaAsOI substrates is currently limited by the long diffusion distances required in a wafer-scale lateral etching process.  We established a model that identifies the rate-limiting processes and potential approaches that lift these constraints and enable this method to be used for fabrication of large-diameter GaAsOI substrates.



Figure 1: GaAsOI fabrication process in this work: 1) Preparation of the bonding substrates: thermally oxidized Si handle wafer and GaAs donor wafer with GaAs/Ge/GaAs epitaxial stack covered with PECVD oxide. Si: dark grey, SiO2: light grey, GaAs: blue, Ge: dark yellow. 2) Low-temperature wafer bonding and room temperature spontaneous etching with XeF2 gas-removing sacrificial Ge layer. 3) After separation, GaAsOI on Si substrate and reclaimed GaAs donor substrate.



Figure 2: XTEM image showing GaAsOI/Si structure with high quality bond interface obtained with our low-temperature fabrication process.




1. C. L. Dohrman, K. Chilukuri, D. M. Isaacson, M. L. Lee, and E. A. Fitzgerald, “Fabrication of silicon on lattice-engineered substrate (SOLES) as a platform for monolithic integration of CMOS and optoelectronic devices,” Materials Science and Engineering B-Solid State Materials for Advanced Technology, vol. 135, pp. 235-237, Dec 15 2006. [↩]
2. W. K. Liu, D. Lubyshev, J. M. Fastenau, Y. Wu, M. T. Bulsara, E. A. Fitzgerald, M. Urteaga, W. Ha, J. Bergman, B. Brar, W. E. Hoke, J. R. LaRoche, K. J. Herrick, T. E. Kazior, D. Clark, D. Smith, R. F. Thompson, C. Drazek, and N. Daval, “Monolithic integration of InP-based transistors on Si substrates using MBE,” Journal of Crystal Growth, vol. 311, pp. 1979-1983, Mar 15 2009. [↩]
3. Y. Bai and E. A. Fitzgerald, “Ge/III-V heterostructures and their applications in fabricating engineered substrates,” Electrochemical Society Transactions, vol. 33, pp. 927-932, 2010. [↩]