All entries for Carl Thompson

Carl V. Thompson

Title: Professor
Department: Department of Material Science and Engineering

Collaborators

W.K. Choi, Prof., National University of Singapore
S.J. Chua, Prof., NUS
J.A. del Alamo, Professor, MIT
C.L. Gan, Prof., Nanyang Technical University
P.M. Gschwend, Prof. ECE, MIT
A.J. Hart, Prof., U. Mich.
Y. Li, Prof., NUS
P.K. Liaw, Prof., U. Tenn.
K.P. O’Brien, Intel
T. Palacios, Prof., EECS, MIT
D.L. Plata, Prof., Mt. Holyoke
P. Rack, Prof. U. Tenn, ONL
Y. Shao-Horn, Prof. MSE, Mech. E, MIT
F. Stellacci, Prof., MSE, MIT
K. Van Vliet, Prof., MSE, MIT
D. Kim, Postdoctoral Research Associate, MSE, MIT
L. Li, Postdoctoral Research Associate, MSE, MIT
G. Nessim, Postdoctoral Res. Assoc.

Graduate Students

A. Al-Obeidi, NSF Fellow, MSE
Y.K. Khoo, SMA Fellow, NTU
G. H. Kim, Res. Asst., MSE
R. Mitchell, Res. Asst., MSE
W. Sasangka, SMA Fellow, NTU
J. Ye, Res. Asst., MSE
H. Yu, Res. Asst., MSE
Z. Wen, Res. Asst., MIT
L. Zhang, Visiting Student, MSE

Support Staff

K. Fitzgerald, Admin. Asst. II

Publications

G.D. Nessim, D. Acquaviva, M. Seita, K.P. O’Brien, and C.V. Thompson, The Critical Role of the Underlayer Material and Thickness in Grown Vertically Aligned Carbon Nanotubes and Nanofibers on Metallic Substrates by Chemical Vapor Deposition, Adv. Funct. Mat. 20, 1306 (2010).

J. Yun, Rui Wang, W.K. Choi, J.T.L. Thong, C.V. Thompson, Mei Zhu, Y.L. Foo, M.H. Hong, Field emission from a large area of vertically-aligned carbon nanofibers with nanoscale tips and controlled spatial geometry, Carbon 48, 1362 (2010).

Q. Guo, J. Noh, P.K. Liaw, P.D. Rack, Y. Li, C.V. Thompson,Density change upon crystallization in amorphous Zr-Cu-Al thin films, Acta Materialia 58, 3633 (2010).

S.-W. Chang, J. Oh, S.T. Boles, C.V. Thompson, Fabrication of Silicon Nanopillar-based Nanocapacitor Arrays, Appl. Phys. Letts. 96, 153108 (2010).

P. Makaram, J. Joh, J.A. del Alamo, T. Palacios, and C.V. Thompson, Evolution of structural defects associated with electrical degradation in AlGaN/GaN high electron mobility transistors, Appl. Phys. Lett. 96, 233509 (2010).

J. Yun, Rui Wang, M. H. Hong, J. T. L. Thong, Y. L. Foo, C. V. Thompson, and W. K. Choi, Converting carbon nanofibers to carbon nanoneedles: catalyst splitting and reverse motion, Nanoscale 2, 2180 (2010).

D. Kim, P. Makaram and C.V. Thompson, Microscale Oscillating Crack Propagation in Silicon Nitride Thin Films, Appl. Pys. Letts. 97, 071902 (2010).

J. Ye and C.V. Thompson, Mechanisms of complex morphological evolution during solid-state dewetting of single-crystal nickel thin films, Appl. Phys. Letts. 97, 071904 (2010).

S.-W. Chang, V.P. Chuang, S.T. Boles, and C.V. Thompson, Metal-Catalyzed Etching of Vertically-Aligned Polysilicon and Amorphous Silicon Nanowire Arrays by Etching Direction Confinement, Adv. Funct. Mat. 20, 4634 (2010).

Q. Guo, L. Zhang, A.S. Zeiger, Y. Li, K.J. Van Vliet, and C.V. Thompson, Compositional dependence of Young’s moduli for amorphous Cu-Zr films measured using combinatorial deposition on microscale cantilever arrays, Scripta Materialia 64, 41 (2011).

J. Leib and C.V. Thompson, Weak Temperature Dependence of Stress Relaxation in As-Deposited Polycrystalline Gold Films, Physical Review B (Rapid Communication) B82, 121402 (2010).

H. Zhang, C.V. Thompson, F. Stellacci and J.T.L. Thong, Parallel fabrication of polymer-protected nanogaps, Nanotechnology 21, 385303 (2010).

J. Ye and C.V. Thompson, Anisotropic edge retraction and hole growth during solid-state dewetting of single crystal nickel thin films, Acta Materialia 59, 582 (2011).

G.D. Nessim, M. Seita, D.L. Plata, PhD; K.P. O’Brien, A.J. Hart, E.R Meshot; C.M. Reddy; P.M Gschwend; C.V Thompson, Precursor gas chemistry determines the crystallinity of carbon nanotubes synthesized at low temperature, Carbon 49, 804 (2011).

J. Ye and C.V. Thompson, Regular pattern formation through the retraction and pinch-off of edges during solid-state dewetting of patterned single crystal films, Phys. Rev. B82, 193408 (2010).

J. Oh and C.V. Thompson, A Tungsten Interlayer Process for Fabrication of Through-pore Anodic Aluminum Oxide Scaffolds on Gold Substrates, J. Eelectrochem. Soc. 158, K11 (2011).

J. Oh and C.V. Thompson, Abnormal Anodic Aluminum Oxide Formation in Confined Structures for Lateral Pore Arrays, J. Electrochem. Soc. 158, C71 (2011).

J. Ye and C.V. Thompson, Templated Solid-State Dewetting to Controllably Produce Complex Patterns, Advanced Materials 23, 1567 (2011).

J. Oh and C. V. Thompson, The role of electric field in pore formation during aluminum anodization, Electrochemica Acta 56, 4044 (2011).

Fabrication of Si Nanowire-Based Capacitors for Power Management

Authors: W. Zheng, A. Al-Olbeidi, C. V. Thompson
Sponsorship: SRC

Capacitors have attracted considerable attention due to their potential as an energy buffer in a hybrid energy system. Improvement of the capacitor performance has been achieved by various approaches, one of which is introducing high surface-to-volume ratio structures to increase the effective electrode area. Therefore, fabrication of Si nanowire arrays and construction of capacitors based on these nanowires have been widely studied. Metal-catalyzed etching (MCE) is a new process to fabricate silicon nanowire arrays by the combination of film patterning techniques and the wet chemical etching step. The MCE technique is more appreciable than others because of its room temperature processing condition, which makes it compatible with current standard silicon integrated circuit fabrication technology. In this process, patterned metal films are used to catalyze the etching of silicon at the metal-silicon interface in a mixed etching of hydrofluoric acid and hydrogen peroxide.

We have recently demonstrated the feasibility of using the MCE to fabricate Si nanowires to make nanocapacitors^[1]. The fabrication process is described schematically in Figure 1. Interference lithography is used to make the anti-dot array pattern on the metal film, and the MCE process finally creates silicon wire arrays. Gold is then removed, and an oxide dielectric layer is grown in a tube furnace. Finally, electrodeposited nickel serves as the other electrode of the capacitor. We have demonstrated a factor of approximately 10 times improvement in the capacitance density over planar devices for nanocapacitors with a 200-nm period and 1.5-µm height. Figure 2 shows the results of capacitance measurements for different period and height pillar height capacitors. Further improvement of silicon nanowire capacitors can be achieved using wires with higher aspect ratios and smaller diameters and spacings.

: Figure 1: Schematic of the nanocapacitor arrays processing.

: Figure 2: Capacitance for different period and pillar height capacitors.

S. W. Chang, J. Oh, S. T. Boles, and C. V. Thompson, “Fabrication of silicon nanopillar-based nanocapacitor arrays,” Applied Physics Letters, vol. 96, p. 153108, 2010. [↩]

Controlling the Intrinsic Stresses in Polycrystalline Metallic Films for N/MEMS Applications

Authors: H. Yu, C. V. Thompson
Sponsorship: NSF

Polycrystalline metallic thin films are vital in a wide variety of applications, including microelectronics, plasmonics, magnetic storage, N/MEMS and catalysis. Because mechanical properties strongly influence their reliability and performance, understanding and controlling the intrinsic stresses in as-deposited films are of great importance. When the capacitance or multi-beam laser technique is used, real-time stress measurements can be performed during thin film deposition. The measurement results do not only provide a useful tool to define the stress evolution history but also an insightful picture for the study of structure evolution processes. When combining the in situ stress measurement with other characterization techniques and theoretical modeling, we are able to move towards a comprehensive understanding of the underlying atomic processes during Volmer-Weber growth.

We have experimentally studied the intrinsic stress evolution at different homologous temperatures. Figure 1 shows the general trend—compressive stress is favored at higher temperatures and tensile stress is favored at lower temperatures. This trend indicates that the compressive stress generation processes are thermally activated. Furthermore, we found the incremental stress changes from compressive to tensile during growth at intermediate homologous temperatures, e.g., Ni at 398K. The origin of the compressive-tensile transition is not known exactly. None of the previous models^[1]^[2]^[3] are able to explain the transition behavior. We have also studied the stress behaviors during long interruptions of gold films. Particularly, we studied the long interruptions of gold films with different thicknesses. Figure 2 demonstrates that the total released stress is dependent on the film thickness during long interruptions. This result strongly suggests that the stress relaxation during long interruptions is a bulk process. Meanwhile, we found abnormal grain growth occurs in as-deposited gold film at room temperature. By calculating the densification stress due to grain growth and comparing its value with the measured bulk relaxation stress, we conclude that grain growth is the main process of bulk stress relaxation.

: Figure 1: Stress-thickness curves of fcc metals at different homologous temperatures.

: Figure 1: Stress-thickness curves of fcc metals at different homologous temperatures.

F. Spaepen,“Interfaces and stresses in thin films,” Acta. Materialia, vol. 48, pp. 31-42, 2000. [↩]
C. Friesen and C.V. Thompson, “Reversible stress relaxation during precoalescence interruptions of Volmer-Weber thin film growth, Physical Review Letters, vol. 89, no. 2, p.126103, Sept. 2002. [↩]
E. Chason, B. W. Sheldon, L. B. Freund, J. A. Floro, and S. J. Heame, “Origin of compressive residual stress in polycrystalline thin films,” Physical Review Letters, vol. 88, no. 15, p. 156103, Apr. 2002. [↩]

Growth and Characterization of Carbon Nanotube Carpets for Electrochemical Applications

Authors: R. R. Mitchell, B. M. Gallant, B. L. Wardle, Y. Shao-Horn, C. V. Thompson
Sponsorship: MITEI, Singapore-MIT Alliance, NSF MRSEC

Improvements in electrochemical devices for energy storage (Li-based batteries and ultracapacitors), and capacitive deionization are being aggressively investigated. There are many benefits to fabricating nanostructured electrodes for these devices^[1]. Carbon nanotube (CNT) arrays show immense promise as electrodes due to the high aspect ratios, electrical conductivity, and mechanical rigidity of CNTs.

Carbon nanotubes are typically grown using transition metal catalysts, such as Fe. The catalyst morphology has a direct influence on the resulting nanotube diameter and areal density. We have demonstrated control of catalyst-coarsening by changing the time of the introduction of H₂ during CVD growth for nanotubes grown on insulating substrates^[2]. This technique allows the modulation of tube properties and carpet morphology. Additionally, we have demonstrated low-temperature growth on conductive substrates, enabled by gas preheating^[3] and rapid sample insertion into the growth zone in concert with an appropriate catalyst-substrate combination^[4]. An example of crystalline tubes grown on conductive substrates is shown in Figure 1.

In order to explore the effect of carpet structure on electrochemical device performance, we can mechanically densify nanotube carpets using a technique developed by Wardle et al^[5]. Further, we have developed a process for transferring carpets, grown on insulating substrates, to arbitrary conductive substrates as illustrated in Figure 2. In addition to investigating densified nanotube carpets, we also plan to explore composite electrode structures for Li-ion batteries composed of CNT-supported nanoparticle Li-intercalation materials.

: Figure 1: Carpet of vertically-aligned CNTs grown on a conductive substrate at 475 °C. The catalyst/underlayer system is Fe/Ta. The HRTEM image on the inset shows the crystalline nature of the CNTs (scale bar 5 nm).

: Figure 2: Vertically aligned CNT carpet transferred to a Au-coated Si substrate via a diffusion-bond transfer, enabling nanotube carpets to be integrated into electrochemical devices.

Y. G. Guo, J. S. Hu, and L. J. Wan, “Nanostructured materials for electrochemical energy conversion and storage devices,” Advanced Materials, vol. 20, pp. 2878-2887, Aug. 2008. [↩]
G. D. Nessim, A. J. Hart, J. S. Kim, D. Acquavia, J. Oh, C. D. Morgan, M. Seita, J. S. Leib, and C. V. Thompson, “Tuning of vertically-aligned carbon nanotube diameter and areal density through catalyst pre-treatment,” Nano Letters, vol. 8, pp. 3587-3593, Nov. 2008. [↩]
G. D. Nessim, M. Seita, K. P. O’Brien, A. J. Hart, R. K. Bonaparte, R. R. Mitchell, and C. V. Thompson, “Low temperature synthesis of vertically aligned carbon nanotubes with electrical contact to metallic substrates enabled by thermal decomposition of the carbon feedstock,” Nano Letters, vol. 9, pp. 3398-3405, Oct. 2009. [↩]
G. D. Nessim, D. Acquaviva, M. Seita, K. P. O’Brien, and C. V. Thompson, “The critical role of the underlayer material and thickness in grown vertically aligned carbon nanotubes and nanofibers on metallic substrates by chemical vapor deposition,” Adv. Funct. Mat., vol. 20, 2010. [↩]
B. L. Wardle, D. S. Saito, E. J. Garcia, A. J. Hart, R. G. de Villoria, and V. P. Verploegen, “Fabrication and characterization of ultrahigh-volume-fraction aligned carbon nanotube-polymer composites,” Advanced Materials, vol. 20, pp. 2707-2714, July 2008. [↩]

Templated Solid-State Dewetting for Pattern Formation

Authors: J. Ye, G. Kim, C. V. Thompson, J. Ye, G. Kim, C. V. Thompson

Vapor deposited thin films are rarely stable, so that when they are heated to temperatures at which atomic diffusivities are sufficiently high, they will dewet to form isolated islands. This liquid-like process, driven by surface energy minimization, can occur well below the film’s melting temperature, so that structure evolution occurs via surface self-diffusion on the solid film. Film dewetting (sometimes called agglomeration) has long been a problem in the processing of micro-systems. Dewetting of silicides, metal films, and even silicon-on-insulator films has been a concern that required careful process control to avoid. At the same time, dewetting has also come to be appreciated as a means of producing catalysts for nanowire and nanotube growth and, increasingly, arrays of more complex structures.

In the past, we have studied dewetting of polycrystalline to understand the conditions required to avoid dewetting, as well as to develop techniques for control of dewetting to give ordered arrays of catalysts. In recent work, we have studied dewetting of single crystal films, using epitaxial Ni films on MgO as a model system. We found that pre-patterning of the films can be used to reproducibly guide the formation of complex structures. Pattern formation is strongly affected by the size of the patterning relative to the film thickness, and by crystalline anisotropy of the surface energy. Shape evolution is governed by a specific set of fundamental processes that include formation and pinch-off of rims to form wires^[1], corner and edge instabilities^[2], edge faceting^[3], and Rayleigh-like instabilities to form islands from lines^[4]. Relatively simple pre-patterning can be used to reproducibly form patterns with more complex shapes and smaller feature sizes.

: Figure 1: Dewetting of square patches patterned from a Ni(110) film. For the first row, the initial pattern edges (indicate by the dashed lines) lay along [100] (vertical) and [1-10] (horizontal) in-plane directions. In the second and third row, the edges lay along [111] directions. Scale bars indicate 10 µm. (Note that the initial patch size was smaller for the third row than for the second row.)

: Figure 2: Dewetting of cross patches with pre-patterned internal circular holes patterned from a Ni(110) film. Dashed lines indicate the initial pattern. Scale bars indicate 10 µm.

J. Ye and C. V. Thompson, “Regular pattern formation through the retraction and pinch-off of edges during solid-state dewetting of patterned single crystal films,” Physics Review, vol. B82, p. 193408, 2010. [↩]
J. Ye and C. V. Thompson, “Mechanisms of complex morphological evolution during solid-state dewetting of single-crystal nickel thin films,” Appl. Phys. Letts., vol. 97, p. 071904, 2010. [↩]
J. Ye and C. V. Thompson, “Anisotropic edge retraction and hole growth during solid-state dewetting of single crystal nickel thin films,” Acta Materialia, vol. 59, p. 582, 2011. [↩]
J. Ye and C. V. Thompson, “Templated solid-state dewetting to controllably produce complex patterns,” Advanced Materials, vol. 23, p. 1567, 2011. [↩]

Silicon Nanowire Arrays for Energy Storage Devices

Authors: A. Al-Obeidi, C. V. Thompson
Sponsorship: MITEI

Material properties are defined not only by the composition, but by structure as well. Such materials are suited for use in electrochemical energy storage such as lithium-ion batteries. Specifically, nanostructured silicon nanowires for use in lithium-battery technologies offer a high surface-to-volume ratio, which translates into enhanced charge/discharge rates in battery systems. Moreover, superior mechanical properties over bulk materials can be also be achieved^[1]^[2].Synthesis of low-cost, room temperature processing of silicon nanowires has been achieved using metal-catalyzed etching (MCE). This process consists of using thin, patterned metal films of gold, which serve as the site of the catalytic etching of silicon. This etch process is carried out in an HF solution with an oxidant such as H₂O₂; etching occurs only at the metal-silicon interface. This enables the creation of large (>1 cm²) arrays of perfectly ordered Si-NWs with periods down to 40 nm, diameters down to 20 nm, and aspect ratios up to 200 to 1 (Figure 1). These novel high-volume filling arrays are being used for studies of lithiation, where silicon serves as anode materials. Silicon has the highest known Li storage capacity, at four Li atoms per Si atoms. Improved silicon nanowire arrays on metal are being pursued to reduce resistance losses and enhance cyclability (Figure 2). Analysis of silicon crystallinity and nanowire geometric configuration is being pursued.^[3]

: Figure 1: An example silicon nanowire array produced using MCE. Wires are 4 µm long and have a diameter of 100 nm.

C. K. Chan, H. Peng, G. Liu, K. McIlwrath, X. F. Zhang, R. A. Huggins, and Y. Cui, “High-performance lithium battery anodes using silicon nanowires,” Nature Nanotechnology, vol. 3, pp. 31-35, 2008. [↩]
C. K. Chan, R. Ruffo, S. S. Hong, R. A. Huggins, and Y. Cui, “Structural and electrochemical study of the reaction of lithium with silicon nanowires,” J. of Power Sources, vol. 14, pp. 34-39, 2010. [↩]
S. W. Chang, V. P. Chuang, S. T. Boles, C. A. Ross, and C. V. Thompson, “Densely-packed arrays of ultrahigh-aspect-ratio silicon nanowire fabricated using block copolymer lithography and metal-assisted etching,” Adv. Funct. Mater., vol. 19, pp. 2495-2500, 2009. [↩]

MTL Annual Research Report 2011