Continuous-time Delta-sigma Analog-to-digital Converters for Application to Multiple-input Multiple-output Systems

  • Authors: D. Yoon, H.-S. Lee
  • Sponsorship: MediaTek, Inc

As wireless communication technology is rapidly advancing, new wireless applications are continuously developed. Figure 1 shows each application space and the required dynamic range[1]. The new wireless applications demand wideband (50 MHz) and high resolution data converters (>14 bits). Delta-sigma (DS) analog-to-digital converters (ADCs) are best suited for their ability to achieve high resolution. However, the large bandwidth required poses a significant challenge. A DS ADC can be implemented in either a discrete-time (DT) or a continuous-time (CT) structure. Since DT DS ADCs require op amp settling within each half clock period, the gain-bandwidth requirement for the op amp is extremely high for the sampling rate required for 50-MHz bandwidth. The CT DS ADCs require much lower gain-bandwidth. Thus, CT DS ADCs can function at a higher sampling frequency and achieve a wider bandwidth than DT DS ADCs. In addition, since the CT DS ADCs are more power-efficient and have an inherent anti-aliasing property, they are more suitable for the demanding new wireless applications.

This project focuses on the design of CT DS ADCs, specifically for their application in multiple-input multiple-output wireless receivers. For this application, each CT DS ADC in a channel must provide wide bandwidth and high dynamic range at low power consumption. The state-of-art CT DS ADCs fail to come close to either wide-enough bandwidth or high-enough dynamic range for such applications[2],[3]. We are investigating a new type of a CT multi-stage noise-shaping (MASH) DS ADC based on a DT sturdy-MASH DS ADC[4]. Figure 2 shows the overall structure of a CT MASH DS ADC. The main advantage of this new type of CT DS ADCs is that it does not require digital filters that conventional MASH DS ADCs need to cancel out the quantization error of the first stage. We have developed several new techniques to make a CT MASH DS ADC faster, more accurate, and robust.

  1. K. Lee, J. Chae, M. Aniya, K. Hamashita, K. Takasuka, S. Takeuchi, and G. C. Temes, “A noise-coupled time-interleaved delta-sigma ADC with 4.2 MHz bandwidth, 98 dB THD, and 79 dB SNDR,” IEEE J. Solid-State Circuits, vol. 43, no. 12, pp. 2601-2612, Dec. 2008. [↩]
  2. Y.-S. Shu, J.-Y. Tsai, P. Chen, T.-Y. Lo, and P.-C. Chiu, “A 28fJ/conv-step CT DS Modulator with 78dB DR and18MHz BW in 28nm CMOS Using a Highly Digital Multibit Quantizer,” ISSCC Dig. Tech. Papers, pp. 268-269, Feb. 2013. [↩]
  3. P. Shettigar and S. Pavan, “A 15mW 3.6GS/s CT-DS ADC with 36MHz Bandwidth and 83dB DR in 90nm CMOS,” ISSCC Dig. Tech. Papers, pp. 156-157, Feb. [↩]
  4. N. Maghari, S. Kwon, and U. Moon, “74 dB SNDR multi-loop sturdy-MASH delta-sigma modulator using 35 dB open-loop Opamp gain,” IEEE J. Solid-State Circuits, vol. 44, no. 8, pp. 2212-2221, Aug. 2009. [↩]

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