A Continuous-Time Bandpass Delta-Sigma Modulator

  • Authors: X. Yang, H.-S. Lee
  • Sponsorship: SRC/FCRP C2S2

Bandpass delta-sigma modulators (BPDSMs) are a good solution for modern receiver systems. They digitize analog signals directly from the intermediate frequency, allowing more flexibility in the digital back end. Figure 1 contrasts a traditional receiver signal processing chain with that of a BPDSM system. In a BPDSM system, high-frequency narrow band signals are converted to digital form without prior down-conversion to baseband[1]. This pushes the signal processing burden to the digital domain and improves both the system’s simplicity and its power efficiency.

BPDSMs can be realized in either continuous-time (CT) or discrete-time (DT) fashion. The CT structure enjoys certain advantages over its DT counterpart[2]: 1) it has the potential to achieve lower noise and better linearity; 2) it relaxes the gain-bandwidth requirement on the op amps; 3) it provides intrinsic anti-alias filtering. Therefore, CTBPDSM provides a more power-efficient solution for wideband and high resolution analog-to-digital conversion.

This project focuses on the design of a CTBPDSM that can achieve a signal-to-noise ratio (SNR) of over 80dB with a signal bandwidth of 25MHz, a sampling rate of 1GHz, and a center frequency at 250MHz. Figure 2 shows the modulator architecture. A cascaded resonator feedback (CRFB) topology is employed to realize a flat in-band signal transfer function. An 8-th order noise transfer function is implemented with four active RC resonators in cascade. The challenge lies in the design of the continuous-time bandpass loop filter with both low power and high linearity requirements. In order for resonators to have high quality factor, op amps need to maintain high gain at the center frequency. To achieve this goal, we adopt a 4-stage op amp with feed-forward gm-C compensation[3]. We have developed techniques to make the op amps more power efficient and stable. We are also investigating Pavan’s method[4], which helps compensate for loop filter non-idealities by tuning feedback coefficients.

  1. R. Schreier and G. C. Temes, Understanding Delta-Sigma Data Converters. Hoboken: John Wiley & Sons. Inc., 2005. [↩]
  2. K. Philips, “Continuous-time Sigma-Delta ADCs,” Philips Research Laboratories, Eindhoven, the Netherlands. [↩]
  3. G. Mitteregger, C. Ebner, S. Mechnig, T. Blon, C. Holuigue, and E. Romani, “A 20-mW 640-MHz CMOS Continuous Time DS ADC With 20-MHz Signal Bandwidth, 80-dB Dynamic Range and 12-bit ENOB,” IEEE Journal of Solid-State Circuits, vol. 41, no. 12, pp. 2641-2649, Dec. 2006. [↩]
  4. S. Pavan, “Systematic Design Centering of Continuous Time Oversampling Converters,” IEEE Transactions on Circuits and Systems – II: Express Briefs, vol. 57, no. 3, pp. 158-162, Mar. 2010. [↩]

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