All entries for Vladimir Stojanovic

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Vladimir Stojanović

• Title: Associate Professor
• Department: Department of Electrical Engineering & Computer Science

Collaborators

• E. Alon, UC Berkeley
• K. Asanovic, UC Berkeley
• T.-J. King Liu, UC Berkeley
• A. Kavcic, U. Hawaii at Manoa
• D. Markovic, UC Los Angeles
• C-K. K. Yang, UC Los Angeles

Graduate Students

• W. An, EECS
• F. Chen, Res. Asst., EECS
• H. Fariborzi, Res. Asst., EECS
• M. Georgas, Res. Asst., EECS
• J. Leu, Res. Asst., EECS
• Y. Li, Res. Asst., EECS
• Z. Li, Res. Asst., EECS
• B. Moss, Res. Asst., EECS
• R. Sredojević, Res. Asst., EECS
• C. Sun, Res. Asst., EECS
• O. Uyar, Res. Asst., EECS

Publications

R. Sredojević and V. Stojanović, “Fully-Digital Transmit Equalizer
with Dynamic Impedance Modulation”, [Invited] IEEE of Journal
Solid-State Circuits, 25 pp., August 2011.

S. Song and V. Stojanović, “A 6.25 Gb/s Voltage-time Conversion Based
Fractionally Spaced Linear Equalization Receiver for High-speed
Links,” IEEE Journal of Solid-State Circuits, vol. 46, no. 5, 15
pages, May 2011.

J. S. Orcutt, S. D. Tang, S. Kramer, H. Li, V. Stojanović, and R. J.
Ram, “Low-Loss Polysilicon Waveguides Suitable for Integration within
a High-Volume Electronics Process,” in Proceedings of Optical Society
of America – CLEO/QELS Conference, Baltimore, MD, 2 pp., May 2011.

S.D. Vamvakos, V. Stojanović, and B. Nikolić, “Discrete-Time, Linear
Periodically Time-Variant Phase-Locked Loop Model for Jitter
Analysis,” IEEE Transactions on Circuits and Systems-I, 16 pp.,
2011.

H. Kam, T.-J. K. Liu, V. Stojanović, D. Marković, and E. Alon, “Design, Optimization, and Scaling of MEM Relays for Ultra-Low-Power Digital Logic,” IEEE Transactions on Electron Devices, vol. 58, no. 1, pp. 236-250, January 2011.

J. S. Orcutt, A. Khilo, C. W. Holzwarth, M. A. Popović, H. Li^, J. Sun, T. Bonifield, R. Hollingsworth, F. X. Kärtner, H. I. Smith, V. Stojanović, and R. J. Ram, “Nanophotonic integration in state-of-the-art CMOS foundries,” Optics Express, vol. 19, no. 3, pp. 2335-2346, January 2011.

M. Spencer, F. Chen, C. Wang, R. Nathanael, H. Fariborzi, A. Gupta, H. Kam, V. Pott, J. Jeon, T-J. K. Liu, D. Marković, E. Alon, and V. Stojanović, “Demonstration of Integrated Micro-Electro-Mechanical Relay Circuits for VLSI Applications,“ IEEE Journal of Solid-State Circuits [Invited], vol. 46, no. 1, pp. 308-320, January 2011.

R. Sredojević, and V. Stojanović, “Digital Link Pre-emphasis with Dynamic Driver Impedance Modulation”, IEEE Custom Integrated Circuits Conference, San Jose, CA, pp. 1-4, September 2010.

F. Chen, A. P. Chandrakasan, and V. Stojanović, “A Low-power Area-efficient Switching Scheme for Charge-sharing DACs in SAR ADCs”, IEEE Custom Integrated Circuits Conference, San Jose, CA, pp. 1-4, September 2010.

F. Chen, A. P. Chandrakasan, and V. Stojanović, “A Signal-agnostic Compressed Sensing Acquisition System for Wireless and Implantable Sensors”, IEEE Custom Integrated Circuits Conference, San Jose, CA, pp. 1-4, September 2010.

H. Fariborzi, M. Spencer, V. Karkare, J. Jeon, R. Nathanael, C. Wang, F. Chen, H. Kam. V. Pott, T-J. K. Liu, E. Alon, V. Stojanović, and D. Marković, “Analysis and Demonstration of MEM-Relay Power Gating”, IEEE Custom Integrated Circuits Conference, San Jose, CA, pp. 1-4, September 2010.

S. Beamer, C. Sun, Y-J. Kwon, A. Joshi, C. Batten, V. Stojanović, and K. Asanović, ”Re-architecting DRAM with Monolithically Integrated Silicon Photonics,” 37th International Symposium on Computer Architecture (ISCA-37), Saint-Malo, France, pp. 129-140, June 2010.

B. Bond, B., Z. Mahmood, R. Sredojević, Y. Li, A. Megretski, V. Stojanović, Y. Avniel, and L. Daniel, “Compact Modeling of Nonlinear Analog Circuits using System Identification via Semi-Definite Programming and Robustness Certification,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, no. 8, pp. 1149-1162, August 2010.

B. Kim and V. Stojanović, “An Energy-Efficient Equalized Transceiver for RC-Dominant Channels,” IEEE Journal of Solid-State Circuits, vol.45, no.6, pp.1186-1197, June 2010.

F. Chen, M. Spencer, R. Nathanael, C. Wang, H. Fariborzi, A. Gupta, H. Kam, V. Pott, J. Jeon, T-J. K. Liu, D. Marković, V. Stojanović, and E. Alon, “Demonstration of Integrated Micro-Electro-Mechanical (MEM) Switch Circuits for VLSI Applications,” IEEE International Solid-State Circuits Conference, San Francisco, CA, pp. 150-151, February 2010.** (Winner of the 2010 ISSCC Jack Raper Award for Outstanding Technology-Directions Paper).

Fully-digital Transmit Equalizer with Dynamic Impedance Modulation

• Authors: R. Sredojević, V. Stojanović
• Sponsorship: SRC/FCRP C2S2, CICS

In today’s large systems-on-a-chip, communication infrastructure such as high-speed I/Os consumes a significant portion of power, limiting the amount left for useful computation ^[1] . The conflicting bandwidth and power scaling requirements have stimulated vigorous research activities resulting in significant improvements in link energy-efficiency ^{[2] [3]} . These improvements in energy-efficiency have focused on the most dominant sub-systems, such as the clocking and signaling transmit‑receive chain. To that end, voltage-mode (VM) drivers have been introduced instead of current-mode (CM) drivers to improve the energy-efficiency of the transmitter ^{[2] [3]} . However, these VM drivers suffer from a power penalty when used to implement a transmit pre-emphasis filter ^[2] , which is particularly well suited for asymmetric-complexity link channel applications such as memory interfaces ^[4] and lossy channels with long intersymbol-interference (ISI) tails such as cables or silicon carriers ^[5] .

In this work, we show that the power penalty incurred by the traditional driver topologies can be tied to the channel impedance matching constraints. Analysis reveals that power-efficiency improvements over the VM transmit-equalization scheme must come from the controlled relaxation of impedance matching constraints on common‑mode and/or differential‑mode matching. One design that makes such a tradeoff, with frequency-selective common‑mode matching for improved power efficiency, appears in ^[6] . Going a step further, we re-examine the benefits of the static differential impedance matching, and analyze the possible tradeoffs if this constraint is removed, showing that the most efficient driver topology is based on dynamic resistance-modulation (RM) of transmitter impedance.

A test chip fabricated in a 90–nm CMOS process shows relatively small signal degradation from dynamic modulation of driver output impedance over a variety of 20” backplanes at 4 Gb/s, with energy-efficiency of  2pJ/bit at 100 mV of receiver eye, in Figure 1. Despite the signal degradation due to impedance mismatch in its operation, the RM driver compares favorably with the traditional driver topologies (CM and different forms of VM driver) in terms of power efficiency, Figure 2, while allowing for a very compact, fully-digital, implementation.



Figure 1: Energy-efficiency of the RM driver, running at 4 Gb/s, over various backplane channels with Nyquist frequency loss of 8 dB to 12 dB.



Figure 2: Efficiency comparison between the RM driver and the VM/VM*, assuming appropriately scaled and regulated supply for each driver.




1. J. L. Shin, K. Tam, D. Huang, B. Petrick, H. Pham, C. Hwang, H. Li, A. Smith, T. Johnson, and F. Schumacher, “A 40nm 16-core 128-thread CMT SPARC SoC processor,” IEEE Journal of Solid State Circuits, vol. 46, p. 131–144, 2011. [↩]
2. H. Hatamkhani and R. Drost, “A 10-mW 3.6-Gbps I/O transmitter,” 2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408), 2003, pp. 97-98. [↩] [↩] [↩]
3. J. Poulton, R. Palmer, A. Fuller, T. Greer, J. Eyles, W. Dally, M. Horowitz, I. Rambus, and C. Hill, “A 14-mW 6.25-Gb/s transceiver in 90-nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 42, p. 2745–2757, 2007. [↩] [↩]
4. K. Chang, H. Lee, J.-H. Chun, T. Wu, T. J. Chin, K. Kaviani, J. Shen, X. Shi, W. Beyene, Y. Frans, B. Leibowitz, N. Nguyen, F. Quan, J. Zerbe, R. Perego, F. Assaderaghi, E. C. Real, and L. Altos, “A 16Gb/s/link, 64GB/s bidirectional asymmetric memory interface cell,” 2008 IEEE Symposium on VLSI Circuits, June 2008, pp. 126-127. [↩]
5. B. Kim, Y. Liu, T. O. Dickson, J. F. Bulzacchelli, and D. J. Friedman, “A 10-Gb/s compact low-power serial I/O with DFE-IIR equalization in 65-nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 44, no. 12, pp. 3526–3538, Dec. 2009. [↩]
6. W. D. Dettloff, J C. Eble, L. Luo, P. Kumar, F. Heaton, T. Stone, and B. Daly, “A 32mW 7.4 Gb/s protocol-agile source-series-terminated transmitter in 45nm CMOS SOI,” Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International, IEEE, pp. 370–371. [↩]

Design and Demonstration of Integrated Micro-electro-mechanical (MEM) Relay Power Gating

• Authors: H. Fariborzi, F. Chen, M. Spencer, R. Nathanael, C. Wang, A. Gupta, H. Kam, V. Pott, J. Jeon, T. K. Liu, D. Markovic, E. Alon, V. Stojanovic
• Sponsorship: DARPA, NSF, SRC/FCRP C2S2, Berkeley Wireless Research Center, SRC/FCRP MSD

Power gating has become ubiquitous in ICs to reduce the power consumed by inactive CMOS logic circuits. However, the finite I_on/I_off ratio of MOSFET power gates limits their ability to reduce off-state leakage. In contrast, as described in ^{[1] [2]} , micro-electro-mechanical- (MEMS-) based power gates that mechanically make or break electrical contact can completely eliminate off-state leakage (Figure 1). The leakage benefits of MEMS-based power gates may be outweighed by increased switching energy and voltage droop due to relatively large device dimensions and/or operating voltages and on-state resistance. A simple analysis is presented to predict the conditions under which electrostatically-actuated MEM relays can achieve energy savings over MOSFETs for power gates ^[3] . This analysis shows that even in their current state of technology  (~100-μm device pitch), MEM relays can provide energy-reduction benefits over MOSFET power gates for off-periods > 500 μs. With relays scaled to current mass-produced MEMS device dimensions (~ 20 μm), the minimum off-period for energy-reduction benefit reduces to 10 µs.

Relay reliability is improved by the use of hard metals, which results in relatively high contact resistance. For a given relay size, this resistance limits the current density that an array of relay power gates can deliver while maintaining the optimal voltage drop. Current relays can deliver up to ~1 mA/mm² current density. However, power gates built from moderately scaled relays would support > 10-100 mA/mm² and would still fit into the same area as the CMOS chip they are driving. The relays could therefore be post-fabricated on top of the chip or integrated into the backend metallization layers with no penalty in the overall die area.

To experimentally demonstrate the feasibility of power-gating with current relay technology, we applied MEM relay power gating to a 90-nm CMOS chip operating at VDD = 0.6-1 V (Ion = 10-25 µA). Figure 2 illustrates the waveforms of the MEM relay power-gating this chip with MEM gate voltages V_G swinging between 5 and 7 V, with the inset indicating the chip’s correct I/O activity during T_on.



Figure 1: SEM, diagram, and operating states of the MEM relay device.



Figure 2: Schematic and measured waveforms for MEM relay-gated CMOS chip.




1. H. Kam, T.K. Liu, E. Alon, M. Horowitz “Circuit level requirements for MOSFET replacement devices,” in IEDM Tech. Dig. 2008. [↩]
2. F. Chen, M. Spencer, R. Nathanael, C. Wang, H. Fariborzi, A. Gupta, H. Kam, V. Pott, J. Jeon, T.K. Liu, D. Markovic, V. Stojanovic, E. Alon “Demonstration of integrated micro-electro-mechanical switch circuits for VLSI applications,” in International Solid-State Circuits Conference (ISSCC Tech. Dig.), pp. 150-151, Feb. 2010. [↩]
3. H. Fariborzi, M. Spencer, V. Karkare, J. Jeon, R. Nathanael, C. Wang, F. Chen, H. Kam, V. Pott, T.K. Liu, E. Alon, V. Stojanovic, D. Markovic,  “Analysis and demonstration of MEM-relay power gating,” in IEEE Custom Integrated Circuits Conference (CICC), 2010 [↩]

Compressed Sensing for Implantable Sensors

• Authors: F. Chen, A. P. Chandrakasan, V. M. Stojanović
• Sponsorship: CICS

Implantable medical sensors are an emerging application area that exemplifies the stringent energy constraints imposed on wireless sensor circuits. In typical circuit blocks used for medical monitoring, the cost to wirelessly transmit data is orders of magnitude greater than for any other function. State-of-the-art radio transmitters exhibit energy-efficiencies in the nJ/bit range while every other component consumes at most only 10’s of pJ/bit. This cost disparity suggests that some data reduction strategy at the sensor node should be employed to minimize the energy cost of the system. Existing strategies for implementing integrated data compression or filtering solutions under these constraints largely revolve around detecting and extracting specific signal data ^{[1] [2] [3]} . However, the filtered data often contains limited information. For these signal processing strategies, there is a tradeoff between data reduction, robustness, implementation cost, and the granularity of information captured. In each case, the goal is to minimize the number of bits transmitted (to minimize the average radio power) while reliably preserving the signal information at a minimum implementation cost.

In this work, we introduce the design and implementation of a sensor compression architecture (Figure 1) based on the theory of compressed sensing (CS) ^[4] that offers an improved set of tradeoffs toward achieving this goal. A CS-based sensor system combines the positive qualities of existing data acquisition and compression systems: it provides a flexible and general interface like an analog-to-digital converter (ADC) yet still enables data compression proportional to the signal information content, which is consistent with the performance of source coding. For wireless sensor applications, this combination of characteristics is particularly attractive as it would enable a single hardware interface across many applications while simultaneously addressing the energy cost of the wireless telemetry. This approach reduces the average radio power by exploiting signal sparseness to encode the data at a high compression factor (>10x) while enabling a faithful reconstruction of the entire original signal. An efficient implementation of the CS encoder and encoder matrix generation (Figure 2) is realized and demonstrated in a 90-nm CMOS process and consumes 1.9 µW at 0.6 V and 20 kS/s ^[5] .



Figure 1: Block diagram and circuitry for the implementation of the CS linear transform encoder.



Figure 2: Implementation of the CS matrix generation.




1. R. Harrison, P. Watkins, R. Kier, R. Lovejoy, D. Black, B. Greger, and F. Solzbacher, “A low-power integrated circuit for a wireless 100-electrode neural recording system,” IEEE Journal of Solid-State Circuits, vol. 42, pp. 123-133, 2007. [↩]
2. R. Olsson and K. Wise, “A three-dimensional neural recording microsystem with implantable data compression circuitry,” IEEE Journal of Solid-State Circuits, vol. 40, pp. 2796-2804, 2005. [↩]
3. N. Verma, A. Shoeb, J. Bohorquez, J. Dawson, J. Guttag, and A.P. Chandrakasan, “A micro-power EEG acquisition SoC with integrated feature extraction processor for a chronic seizure detection system,” IEEE Journal of Solid-State Circuits, vol. 45, pp. 804-816, 2010. [↩]
4. D. Donoho, “Compressed sensing,” IEEE Transactions on Information Theory, vol. 52, pp. 1289–1306, 2006. [↩]
5. F. Chen, A.P. Chandrakasan, and V. Stojanovic, “A Signal-agnostic compressed sensing acquisition system for wireless and implantable sensors,” presented at IEEE Custom Integrated Circuits Conference, San Jose, CA, 2010. [↩]