MTL Annual Research Report 2011

Implantable medical sensors are an emerging application area that exemplifies the stringent energy constraints imposed on wireless sensor circuits. In typical circuit blocks used for medical monitoring, the cost to wirelessly transmit data is orders of magnitude greater than for any other function. State-of-the-art radio transmitters exhibit energy-efficiencies in the nJ/bit range while every other component consumes at most only 10’s of pJ/bit. This cost disparity suggests that some data reduction strategy at the sensor node should be employed to minimize the energy cost of the system. Existing strategies for implementing integrated data compression or filtering solutions under these constraints largely revolve around detecting and extracting specific signal data ^{[1] [2] [3]} . However, the filtered data often contains limited information. For these signal processing strategies, there is a tradeoff between data reduction, robustness, implementation cost, and the granularity of information captured. In each case, the goal is to minimize the number of bits transmitted (to minimize the average radio power) while reliably preserving the signal information at a minimum implementation cost.

In this work, we introduce the design and implementation of a sensor compression architecture (Figure 1) based on the theory of compressed sensing (CS) ^[4] that offers an improved set of tradeoffs toward achieving this goal. A CS-based sensor system combines the positive qualities of existing data acquisition and compression systems: it provides a flexible and general interface like an analog-to-digital converter (ADC) yet still enables data compression proportional to the signal information content, which is consistent with the performance of source coding. For wireless sensor applications, this combination of characteristics is particularly attractive as it would enable a single hardware interface across many applications while simultaneously addressing the energy cost of the wireless telemetry. This approach reduces the average radio power by exploiting signal sparseness to encode the data at a high compression factor (>10x) while enabling a faithful reconstruction of the entire original signal. An efficient implementation of the CS encoder and encoder matrix generation (Figure 2) is realized and demonstrated in a 90-nm CMOS process and consumes 1.9 µW at 0.6 V and 20 kS/s ^[5] .