All entries for Lan Wei

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Virtual-source-based Self-consistent Charge and Transport Models for Ballistic MOSFETs

• Authors: L. Wei, O. Mysore, D. A. Antoniadis
• Sponsorship: SRC/FCRP MSD, DARPA

Compact models describing the voltage-dependent terminal current and charges (or equivalently, capacitances) are essential for small-signal and transient circuit simulation.  In this work, we extend the virtual-source (VS)-based transport model ^[1] with a self-consistent channel charge model for quasi-ballistic or fully ballistic devices, when the gradual channel approximation (GCA) and the drift transport theory are no longer valid. From a parabolic channel potential profile approximation and current continuity boundary condition, we derive a voltage-dependent charge model that is self-consistent with the transport model in the ballistic regime. The extended VS model has been implemented in Verilog-A language. ^[2]

Devices operating in the ballistic regime in saturation have less channel charge than predicted by the drift-diffusion theories, which is in principle advantageous from the performance point of view.  The quasi-ballistic (QB) model predicts 61% and 58% fewer intrinsic channel charges than the saturation velocity model (Vsat) and non-saturation drift velocity model (NVsat), respectively (Figure 1).  The difference diminishes in the linear region or because the device essentially operates with low carrier velocity and a lot of scattering with low V_gs or V_ds.   It is also shown that the benefits of fast carrier transport in tight-pitch logic circuits diminish due to the presence of extrinsic charges, particularly at higher fan-outs. As shown in Figure 2, the stage delay of a 5-stage ring oscillator predicted by QB model is only 5% and 3% less than that by Vsat and Nsat models, respectively. However, for RF applications the benefit of quasi-ballisticity in Si or near-full ballisticity in III-V HEMTs calculated by the model can be significant.



Figure 1: Channel charges associated with the gate terminal under different charge models without extrinsic capacitances. QB model predicts a 61% and 58% less intrinsic channel charge than Vsat and NVsat models at V_ds=V_gs=1V, respectively.



Figure 2: Stage delay of a 5-stage ring oscillator with different charge models. QB model predicts only a 5% and 3% less delay than Vsat and NVsat models, respectively.




1. A. Khakifirooz, O. Nayfeh, and D. Antoniadis, “A simple semiempirical short-channel MOSFET current-voltage model continuous across all regions of operation and employing only physical parameters,” IEEE Transactions on Electron Devices,, vol. 56, pp. 1674-1680, 2009. [↩]
2. L. Wei, O. Mysore, and D. Antoniadis, “Virtual-source based self-consistent charge and transport models for near-ballistic FETs,” to be submitted to 2011 International Electron Devices Meeting. [↩]

Energy-delay Trade-off for Devices with Asymmetric n-type and p-type Current Drives from a Static-CMOS Circuit-level Perspective

• Authors: L. Wei, D. A. Antoniadis
• Sponsorship: SRC/FCRP MSD, DARPA

Historically, digital logic devices are benchmarked by the on-state current (I_on) at specified off-state current (I_off) and supply voltage (V_dd) at each technology node.  Emerging device technologies are often targeted to outperform Si MOSFETs at the same I_off and V_dd.  Some emerging technologies, such as III-V transistors and Ge transistors, have great advantages in either n-type or p-type devices, instead of both types, at the device level in terms of I_on.  However, recent work [1] shows that devices optimized based on the conventional device-level I_on methodology may not necessarily give the best performance at the circuit-level.  In this work, we extend the methodology proposed in  ^[1] to study the technologies with asymmetric n-type and p-type driving capabilities from a circuit-level perspective.

Circuit-level delay and energy are calculated following the strategies described in ^[1] , assuming static CMOS logic gates.  The smaller of the widths of nMOS (W_n) and pMOS (W_p) is fixed to be 1 mm. Assuming the same pull-up and pull-down delay, the P/N ratio (k=W_p/W_n), is adjusted according to the on-current.   Figure 1(a) minimizes energy per switch at each delay point for selected P/N ratio, with a pMOS and nMOS transporting 10x and 1x current of the 11-nm projection device in ^[1] at the same bias.   The corresponding dynamic energy (E_dyn­) over total energy (E_tot) is shown in Figure 1(b).   It is shown that the optimal sizing ratio is not necessarily 1/10 as in following the conventional sizing scheme.  In fact, the optimal k is the smallest number that can maintain E_dyn at around 80% of E_tot.  As Figure 2 shows, compared with the baseline technology with symmetric nMOS and pMOS, the technology that improves the transport capability of only one type of devices hardly benefits the circuit-level energy-delay trade-off.




Figure 1: (a) Minimum energy per switch and the corresponding (b) E_dyn/E_tot for a circuit application, assuming static-CMOS logic, with a logic depth of 20 and activity factor of 0.01, at selected P/N ratios. The pMOS and nMOS transporting 10x and 1x current of the 11-nm projection device in ^[1] at the same bias. When the penalty of static leakage power, which is proportional to I_off, increases to assure the driving speed, i.e., E_dyn/E_tot decreases to be much less than 80%, the size of the weaker transistor should be increased to suppress the penalty.



Figure 2: The minimum energy per switch as a function of delay, with k as a free variable, for technologies with different strengths of nMOS and pMOS with the 11-nm ITRS projection in ^[1] as the nominal technology.




1. L. Wei, S. Oh, and H. –S. Philip Wong, “Performance benchmarks for Si, III-V, TFET, and carbon nanotube FET – Re-thinking the technology assessment methodology for complementary logic applications,” 2010 IEEE International Electron Devices Meeting, pp. 16.2.1-16.2.4, San Francisco, CA, Dec. 2010 [↩] [↩] [↩] [↩] [↩]