All entries for Duane Boning

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Duane S. Boning

• Title: Professor
• Department: Department of Electrical Engineering & Computer Science

Collaborators

• Y.-C. Lam, NTU, Singapore
• A. Philipossian, Univ. of Arizona

Graduate Students

• K. Balakrishnan, Res. Asst., EECS
• A. Chang, Res. Asst., EECS
• W. Fan, Res. Asst., EECS
• C. GoGwilt, Res. Asst., EECS
• J. Lee, Res. Asst., EECS
• J. Johnson, Res. Asst., EECS
• L. Yu, Res. Asst., EECS

Support Staff

• M. Whiting, Admin. Asst. II

Publications

W. Fan, D. Boning, L. Charns, H. Miyauchi, H. Tano, and S. Tsuji, “Study on Stiffness and Conditioning Effects of CMP Pad Based on Physical Die-level CMP Model,” J. Electrochem. Soc., vol. 157, no. 5, pp. H526-H533, May 2010.

H. Taylor, M. Hale, Y. C. Lam, and D. Boning, “A method for the accelerated simulation of micro-embossed topographies in thermoplastic polymers,” J. Micromechanics and Microengineering, vol. 20, no. 6, p. 065001, June 2010.

H. Taylor, Y. C. Lam, and D. Boning, “An investigation of the detrimental impact of trapped air in thermoplastic micro-embossing,” J. Micromechanics and Microengineering, vol. 20, no. 6, p. 065014, June 2010.

N. Drego, A. Chandrakasan, D. Boning, and D. Shah, “Reduction of Variation-Induced Energy Overhead in Multi-core Processors,” IEEE Trans. on Computer-Aided Design, vol. 30, no. 6, pp. 891-904, June 2011.

H. Taylor, K. Smistrup, and D. Boning, “Modeling and simulation of stamp deflections in nanoimprint lithography: exploiting backside grooves to enhance residual layer thickness uniformity,” Microelectronic Engineering, vol. 88, no. 8, pp. 2154-2157, August 2011.

H. Taylor, D. Boning, and C. Iliescu, “A razor-blade test of the demolding energy in a thermoplastic embossing process,” Journal of Micromechanics and Microengineering, vol. 21, no. 6, p. 067002, June  2011.

R. K. Jena, H. K. Taylor, Y. C. Lam, D. S. Boning, and C. Y. Yue, “Effect of polymer orientation on pattern replication in a micro-hot embossing process: experiments and numerical simulation,” Journal of Micromechanics and Microengineering, vol. 21, no. 6, p. 065007, June  2011.

H. Taylor, K. Smistrup, and D. Boning, “Modeling and simulation of stamp deflections in nanoimprint lithography: exploiting backside grooves to enhance residual layer thickness uniformity,” 36^th International Conference on Micro & Nano Engineering (MNE2010), Genoa, Sept. 2010.

W. Fan, J. Johnson, and D. S. Boning, “Non-Ohmic Wafer-Level Modeling of Electrochemical-Mechanical Planarization (ECMP),” International Conference on Planarization Technology (ICPT), Phoenix, AZ, Oct. 2010.

D. Boning, A. Kahng, H. Taylor, and Y.-K. Wu, “Chip-Scale Simulation of Residual Layer Thickness Uniformity in Thermal Nanoimprint Lithography: Evaluating Stamp Cavity-Height and ‘Dummy-Fill’ Selection Strategies,” 9^th International Conference on Nanoimprint and Nanoprint Technology (NNT), Copenhagen, Denmark, Oct. 2010.

H. Taylor, K. Simstrup, and D. Boning, “Modeling the Enhancement of Nanoimprint Stamp Bending Compliance by Backside Grooves: Mitigating the Impact of Wafer Nanotopography on Residual Layer Thickness,” 9^th International Conference on Nanoimprint and Nanoprint Technology (NNT), Copenhagen, Denmark, Oct. 2010.

J. O. Diaz, H. K. Taylor, R. J. Shul, R. L. Jarecki, T. M. Bauer, D. S. Boning, and D. L. Hetherington, “A Computationally Simple, Wafer-to-Feature-Level Model of Etch Rate Variation in Deep Reactive Ion Etching,” AVS 57^th International Symposium & Exhibition, Albuquerque, NM, Oct. 2010.

K. Balakrishnan, K. Jenkins, and D. Boning, “A Simple Array-Based Test Structure for the AC Variability Characterization of MOSFETs,” IEEE International Symposium on Quality Electronic Design (ISQED), March 2011.

A. H. Chang, D. Boning, and H.-S. Lee, “Redundancy in SAR ADCs,” Great Lakes Symposium on Very Large Scale Integration (GLSVLSI), Lausanne, Switzerland, May 2011.

K. Balakrishnan, K. A. Jenkins, and D. Boning, “A Ring Oscillator-Based Test Structure for AC Variability Characterization of Individual MOSFETs,” 2^nd European Workshop on CMOS Variability (VARI), 4 pages, Grenoble, France, May 2011.

Fan, W., J. Johnson, and D. Boning, “Wafer-level Modeling of Electrochemical-Mechanical Planarization (ECMP),” International Conference on Planarization Technology (ICPT), Phoenix, AZ, Oct. 2010.

W. Fan, D. Boning, Y. Zhuang, Y. Sampurno, A. Philipossian, D. Hooper, and M. Moinpour, “Characterization of CMP Pad Surface Properties,” Clarkson Workshop on Chemical-Mechanical Polishing, Lake Placid, NY, Aug. 2010.

D. Boning, A. H. Chang, K. Zuo, J. Wang, and D. Yu, “Test Structures, Circuits, and Extractions Methods for Determining Pattern Density Effects,” IEEE/ACM Workshop on Variability Modeling and Characterization (VMC), San Jose, CA, Nov. 11, 2010.

Automated Passive Dynamical Model Extraction of Thin Film Bulk Acoustic Resonators (FBAR) for Time Domain Simulations

• Authors: Z. Mahmood, J. Lee, D. S. Boning, L. Daniel
• Sponsorship: SRC/FCRP IFC

Thin Film Bulk Acoustic Resonators (FBARs) are widely used in the design of modern radio frequency components including duplexers, filters, and oscillators. The overall goal of this project is to incorporate the performance parameters of these resonators into the design flow of the overall system. As a first step, the frequency response of the fabricated devices is measured. Traditionally, an equivalent circuit is then built based on least squares fitting of the frequency response of a simple RLC network to the measured data ^[1] . Such a technique is fairly simple, and the resulting equivalent model does capture important performance parameters, such as quality factor and resonant frequency. However, this technique cannot capture spurious resonances and other second order effects, which quite often play a significant role in the overall performance of the device.

In this work, we are developing tools that will automatically generate accurate, compact, and passive dynamical models for FBARs. Given measured transfer function samples, we identify a rational transfer function model that minimizes the mismatch at the given frequencies. These dynamical models can be interfaced with commercial circuit simulators for time domain simulations of a larger interconnected system. To guarantee the stability of the overall simulation, we ensure the passivity of our generated models by enforcing semidefinite constraints during the fitting process as proposed in ^[2] . Figure 1 shows the 3D layout of an FBAR. Numerical results are presented for resonators configured to constitute a bandpass frequency response. Figure 2 compares the output of our identified models with the given measured data.



Figure 1: (Courtesy of Coventor) 3D layout of FBAR.



Figure 2: Plot demonstrating the accuracy of our identified model. We compare measured Z parameters (green dots) with the output from our dynamical model (red solid lines). The plot is zoomed-in at the resonances. (Top: real part. Bottom: imaginary part.)




1. R. C. Ruby, P. Bradley, Y. Oshmyansky, A. Chien, and J.D. Larson, III, “Thin film bulk wave acoustic resonators (FBAR) for wireless applications,” Ultrasonics Symposium, 2001 IEEE, vol.1, no., pp. 813-821. [↩]
2. Z. Mahmood and L. Daniel, “Circuit synthesizable guaranteed passive modeling for multiport structures,”in Proc. Behavioral Modeling and Simulation Conference (BMAS), Sept. 2010. [↩]

Circuit for Characterizing TSV Stress-induced Variation

• Authors: L. Yu, D. S. Boning
• Sponsorship: TSMC

As continued scaling becomes increasingly difficult, 3D integration has emerged as a viable solution to achieve higher bandwidth and power efficiency ^[1] . Through-silicon-via (TSV), which directly connects stacked structures die-to-die, is one of key techniques enabling 3D integration. The process steps and physical presence of TSVs, however, may generate stress-induced thermal mismatch between TSVs and silicon bulk. This effect could further perturb the performance of nearby electronic structures, particularly transistors, diodes, and associated circuits.

We propose a comprehensive study to characterize, analyze, and model stress impact on device and circuit performance induced by single and arrayed TSVs and its interaction with polysilicon and shallow-trench-isolation (STI) layout pattern density. A test chip is designed with multiplexing test circuits providing measurement of key parameters of large numbers of devices. These devices under test (DUTs) have layouts that explore a range of TSV and device layout choices in a layout experimental design (DOE). The test chip uses a scan chain approach combined with low-leakage and low-variation switches and Kelvin sensing connections, providing access to detailed analog device characteristics in large arrays of test devices.

The test structures are divided in three regions, as summarized below. (1) The 60×240 DUT transistor arrays are designed to characterize single TSV stress effects and their interactions with the pattern density and local layout pattern. In each region, a radius sampling scheme is proposed with different sampling distances and angles. Test structures are also designed with different Keep-Out-Zone materials and widths. (2) The 512×512 DUT transistor arrays are designed to characterize pattern density and multiple TSV stress effects. Long-range pattern density effects (STI, polysilicon and TSV pattern density) can also be tested in this region. (3) Four ring oscillators (ROs) with different RO spacing and TSV to transistor angle are designed to characterize single TSV stress effects on digital circuits. In each block, 128 groups of 17-stage ring oscillators with constant STI and poly density are designed to characterize TSV stress effects on circuit speed.



Figure 1: Proposed multiple TSV and long-range pattern density induced variation characterization circuit approach for a mixed nMOS and pMOS transistor array.



Figure 2: RO test circuit block.




1. S. Q. Gu et al. “Stackable memory of 3D chip integration for mobile applications.” IEEE International Electron Devices Meeting, vol. 33, no. 4, pp. 1-4, 2008. [↩]

An On-Chip Test Circuit for Characterization of MEMS Resonators

• Authors: J. H. Lee, D. Weinstein, D. S. Boning
• Sponsorship: SRC/FCRP IFC

Electromechanical resonators such as quartz crystals, surface acoustic wave (SAW) resonators, and ceramic resonators have become essential components in electronic systems. However, due to their large footprint and difficulty in integrating with CMOS processes, there has been much interest in developing microelectromechanical systems (MEMS) resonators that achieve comparable performance yet have smaller footprint and are compatible with CMOS. Recently, MEMS resonators have been proposed that overcome physical limitations in traditional resonators to reach frequencies in the GHz range. In addition, they have the potential for compatibility with CMOS, opening up possibilities for new circuits and systems ^[1] . As with other semiconductor devices, with increasing frequency and with decreasing device size into the submicron scale, variability has started to become a critical issue in MEMS resonators. Thus vigorous characterization of important device parameters such as resonant frequencies, quality factors, and variations associated with them has become necessary. However, one of the critical challenges is the lack of a characterization method that is accurate but efficient enough to be used for testing of the large number of devices necessary to acquire accurate statistical distribution of the parameters of interest. This project proposes an on-chip test circuit that can accurately characterize a large number of resonators for variation analysis. The desired test circuit is general enough that it can be used with a wide range of resonators, not limited to specific frequencies or other properties. Previous works have attempted to achieve similar goals, but most of them were restricted to characterization of a single device or a narrow range of properties. The proposed test circuit is based on a transient step response method using a voltage step that can accurately measure the resonant frequencies and the quality factor of devices ^[2] . The circuit employs a sub-sampling method to capture the high-frequency decay signal ^[3] and a simple analog-to-digital converter (ADC) ^[4] allowing complete digital interface, an important feature for test automation.



Figure 1: Excitation circuit consisting of six transistors that allows all measurements necessary for model parameter extraction and can be used with the sub-sampling technique required to sample high-frequency resonator response signal.



Figure 2: System block diagram for integrated MEMS resonator characterization test circuit.




1. D. Weinstein and S. A. Bhave, “The resonant body transistor,” Nano Letters, vol.10, no. 4, pp. 1234-37, 2010. [↩]
2. M. Zhang, N. Llaser, H. Mathias, and F. Rodes, “CMOS offset-free circuit for resonator quality factor measurement,” IEEE Electronic Letters, vol. 46, no. 10, p. 706, May 2010. [↩]
3. R. Ho et al., “Applications of on-chip samplers for test and measurement of integrated circuits,” in Proc. 1998 IEEE Symposium on VLSI Circuits, June, pp. 138-139. [↩]
4. E. Alon, V. Stojanović, and M. A. Horowitz, “Circuits and techniques for high-resolution measurement of on-chip power supply noise,” IEEE Journal of Solid-State Circuits, vol. 40, no. 4, pp. 820-828, Apr. 2005. [↩]

CMP Slurry Abrasive Particle Agglomeration Modeling

• Authors: J. M. Johnson, D. S. Boning
• Sponsorship: SRC/SEMATECH Engineering Research Center for Environmentally Benign Semiconductor Manufacturing

In this work we propose a particle agglomeration model for CMP, to understand the creation and behavior of agglomerated slurry abrasive particles arising during the CMP process. These particles are accepted as a major cause of defectivity and poor consumable utility due to sedimentation ^{[1] [2] [3]} . We believe that the few slurry abrasive particle modeling attempts prior to this work have been focused on showing data-rich qualitative correlations ^[4] , empirically assumed relationships of those correlations on particle size distributions ^[5] , or quantitative correlations of purely mechanistic behavior of agglomerated particles, without considering chemical effects ^{[2] [6]} .

Our proposed model will provide both a qualitative and quantitative description of agglomeration in slurry abrasive particles during CMP that includes the chemical kinetics and mechanistic behaviors of both the slurry abrasive particles and the slurry electrolyte, enabling more accurate process control, increased consumable utility, and possible defectivity reduction. The proposed model considers the slurry composition as a colloidal suspension of charged colloidal silica in an electrically neutral aqueous electrolyte. First, we present a theoretical relationship between the measurable chemical parameters of the slurry’s aqueous electrolyte, the surface potential of the abrasive particles, and the corresponding zeta potential between the agglomerated abrasive particles is presented. Secondly, this zeta potential is used in a modified DVLO interaction potential model to determine the particle interaction potentials due to both the attractive van Der Waals forces and repulsive electrostatic interactions.  Finally, the total interaction potential created is then used to define a stability ratio for slow versus fast agglomeration and corresponding shear-induced agglomeration rate equations between particles; these are used in a discrete population balance framework to describe the final particle size distribution with respect to time and agglomerate composition.

The framework for this new agglomeration model is being further investigated and we are currently developing and conducting experimentation to validate our theoretical model.

1. F.-C. Chang, S. Tanawade, and R. K. Singh, J. Electrochem. Soc., vol. 156, p. H39, 2009. [↩]
2. R. Biswas, Y. Han, P. Karra, P. Sherman, and A. Chandra, J. Electrochem. Soc., vol. 155, pp. D534-D537, 2008. [↩] [↩]
3. Moinpour, A. Tregub, A. Oehler, and K.Cadien, Mater. Res. Bulletin, 766, 2002. [↩]
4. S. Ramarajan, Y. Li, M. Hariharaputhiran, Y.-S. Her, and S. V. Babu, Electrochem. Solid-State Lett., vol. 3, no. 5, pp. 232-234, 2000 [↩]
5. A. R. Mazaheri and G. Ahmadi, J. Electrochem. Soc., vol. 150, pp. G233-G239, 2003. [↩]
6. F.-C. Chang and R. K. Singh, J. Electrochem. Solid-State Lett., vol. 12, pp. H127-H130, 2009 [↩]

Physical Characterization of CMP Pad Properties

• Authors: W. Fan, D. S. Boning
• Sponsorship: SRC/SEMATECH Engineering Research Center for Environmentally Benign Semiconductor Manufacturing

In CMP process, the pad asperity modulus and asperity height are two important properties that affect the planarization results ^[1] . In this work, physical measurements of pad surface modulus (by nanoindentation) and asperity height (by micro profilometry) are performed on a JSR water soluble particle (WSP) pad ^[2] . The pad is used to polish 300-mm TEOS wafers with pad conditioning up to 16 hours. Pad aging effects are tested by comparing the measured results from the same location (23 cm from pad center) on the pad after different polishing times (initial, 8 hours, and 16 hours).

The pad asperity modulus is measured using a Hysitron TriboIndenter ^[3] . Each sample is indented at different depths (50 nm, 100 nm, 150 nm, and 200 nm). Figure 1 shows the measured asperity reduced modulus. There is a strong depth-dependence of the asperity modulus. The asperity modulus decreases when the indent depth increases. However, the asperity modulus is independent of pad aging time. Asperity height distribution of the pad surface is scanned using a Tencor P-10 surface profilometer. Within a scanned region, the exponential distribution [latex]\xi(h)=\frac{1}{\lambda} e ^{-\frac {h}{\lambda}}[/latex]  is applied to fit the large asperity heights, where λ is the characteristic asperity height. Figure 2 shows the extracted characteristic asperity height. No time-dependence of asperity height is found. Pad groove depth is considered to be strongly dependent on the polishing/conditioning time. The pad groove depth is measured using the microscope and positioning control system on the Hysitron TriboIndenter. Pad groove depth decreases from 1.05 mm to 0.65 mm along condition time due to pad wear. In summary, pad surface properties (asperity modulus and asperity height) are approximately uniform during the whole polishing/conditioning time. As a result, the conditioning achieves consistent pad surface properties, although pad material is worn in the process.



Figure 1: Pad asperity modulus. Modulus is measured at four indentation depths for each sample. Error bars indicate one standard deviation based on measurements achieved from a 40 µm × 40 µm testing area.



Figure 2: Characteristic asperity height. Two 500 µm × 500 µm test regions on each sample are scanned. Error bars indicate one standard deviation based on the characteristic asperity heights extracted from two scanned regions on each sample.




1. W. Fan, D. Boning, L. Charns, H. Miyauchi, H. Tano, and S. Tsuji, “Study on Stiffness and Conditioning Effects of CMP Pad Based on Physical Die-Level CMP Model”, J. Electrochem. Soc., vol. 157, no. 5, pp. H526-H533, 2010 [↩]
2. “JSR CMP Pad,” http://www.jsr.co.jp/jsr_e/pd/ec/pdf/cmp_p.pdf, last accessed in June 2011 [↩]
3. D. S. Boning and W. Fan, “Characterization and Modeling of Pad Asperity Response in CMP”, Mater. Res. Soc. Symp. Proc., vol. 1249, pp.1249-E05-04, 2010 [↩]

A Low-power SAR ADC with Redundancy

• Authors: A. H. Chang, H.-S. Lee, D. S. Boning
• Sponsorship: Masdar Institute of Science and Technology

Technology scaling has enabled low-power operations in digital integrated circuits.  Therefore, the trend to move analog-to-digital operations upstream to allow more signal-processing to shift from the analog domain to the digital domain is inevitable. As most real world signals remain analog, the design of high-performance and low-power analog-digital converters (ADCs) plays a key role to the success of future integrated system design. In this research, we focus on designing (1) robust, (2) low-power, and (3) high-performance time-interleaved successive-approximation-registers (SAR) ADCs. The SAR architecture is adopted because of its good digital compatibility and high energy-efficiency while achieving high sampling rates.

The robustness of SAR ADCs is achieved by analyzing the effectiveness of redundancy (digital error correction) ^{[1] [2]} in improving sampling rates and its immunity from incomplete bit settling errors. Analysis shows that the redundancy algorithm does not help improve sampling rate in all SAR ADC designs; instead, the maximum sampling rate depends on the settling time constant (τ) and the relative magnitude of the ADC delay components ^[3] . As shown in Figure 1, in order to benefit from the redundancy algorithm, τ has to be more than 50 ps.

The low-power operation is achieved by combining the merged capacitor switching algorithm ^[4] and split capacitive array ^[5] . The merged capacitor switching algorithm suffers from its sensitivity to the parasitic capacitance on the outputs of the capacitive DAC. The split capacitive array suffers from a 4x loss in signal power to keep voltage below the supply rail on the sub-DAC and the mismatch problem between the fractional bridge capacitor to other capacitors in the DAC. Our design researches and resolves both issues. Our design also incorporated asynchronous on-chip pulse generator to avoid synchronous high power clock distribution circuit on-chip. The overall SAR ADCs architecture is depicted in Figure 2.



Figure 1: Speed improvement from adopting redundancy ^[2] .



Figure 2: Overall SAR ADCs architectures.




1. F. Futtner, “A 1.2V 10b 20MSample/s non-binary successive approximation ADC in 0.13μm CMOS,” in IEEE International of Solid-State Circuit Conference Digest of Technical Papers, pp. 136-137, 2002. [↩]
2. T. Ogawa, H. Kobayashi, M. Hotta, Y. Takahashi, H. San, and N. Takai, “SAR ADC algorithm with redundancy,” in IEEE APCCAS, pp. 268-271, Nov. 2008. [↩] [↩]
3. A. H. Chang, H.-S. Lee, and D. S. Boning, “Redundancy in SAR ADCs,” in Great Lakes Symposium on VLSI, May 2011. [↩]
4. V. Hariprasath, J. Guerber, S.-H. Lee, and U.-K. Moon, “Merged capacitor switching based SAR ADC with highest switching energy-efficiency,” Electronics Letters, vol. 46, pp. 620-621, April 2010. [↩]
5. Y. Chen, X. Zhu, H. Tamura, M. Kibune, Y. Tomita, T. Hamada, M. Yoshioka, K. Ishikawa, T. Takayama, J. Ogawa, S. Tsukamoto, and T. Kuroda, “Split capacitor DAC mismatch calibration in successive approximation ADC,” in IEEE Custom Integrated Circuits Conference, pp. 279 –282, 2009. [↩]

AC Variability Characterization of MOSFETs

• Authors: K. Balakrishnan, D. S. Boning
• Sponsorship: SRC/FCRP IFC

The high-frequency variability characterization of MOSFETs is becoming more necessary due to new process developments such as high-K metal gates, elevated source-drain junctions, strained silicon, and others. Some of the effects of these variability sources can be seen at low frequencies by characterizing MOSFET parameters such as threshold voltage or saturation current. However, the nature of some of these sources of variability may manifest itself only at high frequencies. Two circuits have been designed and implemented to assess the potential manifestations of these short time-scale, or AC, variation sources.

The first circuit is a simple array-based test structure consisting of 128 devices under test (DUTs) whose relative delays are characterized using a logic gate-based delay detector circuit, as shown in Figure 1 ^[1] . The delay measurement technique only requires a single off-chip DC voltage measurement for each DUT. A design-time optimization is performed on each DUT array to ensure that the measured delays of each DUT primarily reflect its AC, or short time-scale, characteristics rather than previously well-studied DC characteristics such as saturation current, threshold voltage, and channel length.

The second circuit, shown in Figure 2, is a ring oscillator (RO)-based test structure which transforms small delay variations into easily measurable digital and DC quantities ^[2] . This enables the calculation of a parameter that primarily reflects the AC, or short time-scale, characteristics of the DUT. An array of such ROs is designed in order to obtain statistics on the DUTs. The array-based circuit and RO-based circuit occupy areas of 400 um x 20 um and 1600 um x 20 um, respectively, and are both implemented in an advanced CMOS PD-SOI technology. Simulations show that both circuits exhibit good sensitivity towards potential AC variation sources in transistors.



Figure 1: Array-based test structure using NMOS devices under test with shared pull-up PMOS device.



Figure 2: Ring oscillator-based test structure using PMOS device under test with frequency measured in “pass” and “wait” modes of operation.




1. K. Balakrishnan, K. Jenkins, and D. Boning, “A simple array-based test structure for the AC variability characterization of MOSFETs,” International Symposium on Quality Electronic Design, San Jose, CA, Mar. 2011, pp. 539-543. [↩]
2. K. Balakrishnan, K. Jenkins, and D. Boning, “A ring oscillator-based test structure for the AC variability characterization of individual MOSFETs,” presented at the 2^nd European Workshop on CMOS Variability, Grenoble, France, May 2011. [↩]