MTL Annual Research Report 2011

The high-frequency variability characterization of MOSFETs is becoming more necessary due to new process developments such as high-K metal gates, elevated source-drain junctions, strained silicon, and others. Some of the effects of these variability sources can be seen at low frequencies by characterizing MOSFET parameters such as threshold voltage or saturation current. However, the nature of some of these sources of variability may manifest itself only at high frequencies. Two circuits have been designed and implemented to assess the potential manifestations of these short time-scale, or AC, variation sources.

The first circuit is a simple array-based test structure consisting of 128 devices under test (DUTs) whose relative delays are characterized using a logic gate-based delay detector circuit, as shown in Figure 1 ^[1] . The delay measurement technique only requires a single off-chip DC voltage measurement for each DUT. A design-time optimization is performed on each DUT array to ensure that the measured delays of each DUT primarily reflect its AC, or short time-scale, characteristics rather than previously well-studied DC characteristics such as saturation current, threshold voltage, and channel length.

The second circuit, shown in Figure 2, is a ring oscillator (RO)-based test structure which transforms small delay variations into easily measurable digital and DC quantities ^[2] . This enables the calculation of a parameter that primarily reflects the AC, or short time-scale, characteristics of the DUT. An array of such ROs is designed in order to obtain statistics on the DUTs. The array-based circuit and RO-based circuit occupy areas of 400 um x 20 um and 1600 um x 20 um, respectively, and are both implemented in an advanced CMOS PD-SOI technology. Simulations show that both circuits exhibit good sensitivity towards potential AC variation sources in transistors.