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Download as PDFMOS Interfaces in the InAs/GaSb System
With the rapid downscaling of CMOS technology, III-V materials have gained much attention due to their high electron mobility. In particular, indium-arsenide and gallium-antimonide are becoming more popular due to their matched lattice constant and their complimentary physical properties, such as bandgap and carrier mobility [1] ; various heterostructure-based high performance field-effect transistors (FET) and tunneling transistors have been proposed [1] [2] . On the other hand, this material system faces challenges due to the poor oxide/semiconductor interface, which results in high interface trap concentration (Dit) and hence Fermi-level pinning [3] [4] . Therefore, understanding the metal-oxide-semiconductor (MOS) interface in this material system is critical. This study investigates atomic-layer-deposited (ALD) Al2O3 on InAs to provide a preliminary understanding of the Al2O3/InAs interface.
On an S-doped n-type InAs substrate, 60 cycles of Al2O3 are deposited at 200°C and 250°C after HCl wet chemical cleaning. Then, a Mo/Pt/Au (30 nm/20 nm/100 nm) gate stack is formed using electron-beam evaporation; the back contact is formed using Ti/Au. Finally, 30s post-metallization annealing in N2 is carried out. Figure 1 shows the normalized capacitance-voltage (C-V) curves of both samples with frequencies varied from 10kHz to 1MHz. The depletion region of the C-V curve is not sharp and deep, as predicted by simulations [5] , which is mainly due to the series capacitance corresponding to Dit. Still, the comparison between the two samples shows that Al2O3 deposited at 200°C yields lower Dit than 250°C. Figure 2 plots the C-V hysteresis of the two samples at 100kHz, which reflects the oxide mobile charge near the interface. The results show that the hysteresis is moderate for both samples and that the ALD dielectric quality is promising. Quantitative analysis of the Dit is ongoing. In summary, InAs/GaSb is a promising heterojunction system, and research is needed to better understand and optimize the dielectric/semiconductor interface.
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- Figure 1: C-V curves of InAs MOSCAP with Al2O3 dielectric deposited at 200°C and 250°C. Higher deposition temperature gives slightly higher dielectric constant of the dielectric. Impact of Dit induced series capacitance dominates the depletion behavior of both samples.
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- Figure 2: Hysteresis in C-V characteristics of both samples at 100KHz. Mobile charge control in both samples is promising, with hysteresis ~100mV.
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