All entries for Rahul Sarpeshkar

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Rahul Sarpeshkar

• Title: Associate Professor
• Department: Department of Electrical Engineering and Computer Science

Research Scientist

• L. Turicchia, EECS

Postdoctoral Associate

• R. Danial, EECS

Graduate Students

• S. Arfin, Res. Asst., EECS
• W. Wattanapanitch, Res. Asst., EECS
• B. Rapoport, Res. Asst., EECS
• S. S. Woo, Res. Asst., EECS
• A. Lewine, Research Student, EECS

Support Staff

• S. Davco, Admin. Asst.

Publications

L. Turicchia, B. Do Valle, J. Bohorquez, W. Sanchez, V. Misra, L. Fay, M. Tavakoli, and R. Sarpeshkar, “Ultra Low Power Electronics for Cardiac Monitoring,” Invited Paper, IEEE Transactions on Circuits and Systems I. Vol. 57, No. 9, pp. 2279-2290, 2010.

K. H. Wee, L. Turicchia, and R. Sarpeshkar, “Speech-coding strategies for speech prostheses,” Program No. D.18, Brain-Machine Interface, 2010 Neuroscience Meeting, San Diego, CA, Society for Neuroscience, 2010.

B. I. Rapoport, W. Wattanapanitch, L. Turicchia, and R. Sarpeshkar, “Implantable neural decoding systems,” Program No. D.18, Brain-Machine Interface, 2010 Neuroscience Meeting, San Diego, CA, Society for Neuroscience, 2010.

W. Wattanapanitch, D. Kumar, B. Do Valle, L. Turicchia, B. I. Rapoport, S. K. Arfin, S. Mandal, E. Hwang, R. A. Andersen, R. Sarpeshkar, “An ultra-low-power 32-channel wireless neural recording interface,” Program No. D.18, Brain-Machine Interface, 2010 Neuroscience Meeting, San Diego, CA, Society for Neuroscience, 2010.

K. H. Wee, L. Turicchia, R. Sarpeshkar, “An Articulatory Speech-Prosthesis System,” Proceedings of the IEEE International Conference on Body Sensor Networks (BSN 2010), pp. 133-138, 7-9 June 2010.

S. Mandal, R. Sarpeshkar, “A Bio-Inspired Cochlear Heterodyning Architecture for an RF Fovea,” Circuits and Systems I: Regular Papers, IEEE Transactions on, Vol. PP, No. 9, pp. 1-14, 2011.

B. Do Valle, C. T. Wentz, R.  Sarpeshkar, “An Area and Power-Efficient Analog Li-Ion Battery Charger Circuit,” Biomedical Circuits and Systems, IEEE Transactions on, Vol. PP, No. 99, 2011.

A Low-power 32-channel Digitally-programmable Neural Recording System

• Authors: W. Wattanapanitch, R. Sarpeshkar
• Sponsorship: National Institutes of Health

We have designed an ultra-low-power 32-channel neural recording system in a 0.18-µm CMOS technology. The system consists of eight neural recording modules; each module contains four neural amplifiers, an analog multiplexer, an A/D converter, and a serial programming interface. Each amplifier can be programmed to record either spikes or LFPs with a programmable gain from 49-66 dB. To minimize the total power consumption, an adaptive-biasing scheme is utilized to adjust each amplifier’s input-referred noise to suit the background noise at the recording site. The amplifier’s input-referred noise can be adjusted from 11.2 µV_rms (total power of 5.4 µW) down to 5.4 µV_rms (total power of 20 µW) in the spike recording setting. The ADC in each recording module digitizes the signal from each amplifier at 8-bit precision with a sampling rate of 31.25 kS/s per channel and an average power consumption of 483 nW per channel. It achieves an ENOB of 7.65, resulting in a net efficiency of 77 fJ/State, making it one of the most energy-efficient designs for neural recording applications. The presented system was successfully tested in an in-vivo wireless recording experiment from a behaving primate with an average power dissipation per channel of 10.1 µW. The neural amplifier and the ADC occupy the areas of 0.03 mm² and 0.02 mm², respectively, making our design simultaneously area-efficient and power-efficient.



Figure 1: System architecture of the 32-channel neural recording IC.



Figure 2: Superimposed digitized neural waveforms from one of the recording channels.




1. W. Wattanapanitch and R. Sarpeshkar, “A low-power 32-channel digitally-programmable neural recording system,”  IEEE Transaction on Biomedical Circuits and Systems, 2011, accepted for publication.