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Luca Daniel

• Title: Emanuel E. Landsman Associate Professor
• Department: Department of Electrical Engineering and Computer Science

Collaborators

• R. Suaya, Mentor Graphics
• A. Elfadel, IBM T.J.Watson
• R. Mathur, Intel
• E. Demircan, Freescale
• S. Talocia, Politec. di Torino
• P. Triverio, Politec. di Torino
• M. Silveira, Univ. of Lisbon
• J. Villena, Univ. of Lisbon
• H. Fernandez, Univ. of Lisbon
• G. Antonini, Univ. dell’Aquila
• F. Ferranti, Ghent University
• A. Hochman, MIT EECS
• A. Megretski, MIT EECS
• D. Boning, MIT EECS
• J. White, MIT EECS
• K. Van Vliet, MIT Material Sci.
• R. Mahmoodian, MIT Material Sci.
• E. Adalsteinsson, MIT HST
• L. Wald, MGH Harvard

Graduate Students

• Y. Hsiao, MIT EECS
• E. Natarajan, MIT EECS
• Z. Mahmood, MIT EECS
• O. Mysore, MIT EECS
• Z. Zhang, MIT EECS
• Y. Zhao, MIT EECS

Support Staff

• C. Collins, Admin. Asst.

Publications

Z. Mahmood, T.Moselhy, L. Daniel, “Passive Reduced Order Modeling of Multiport Interconnects via Semidefinite Programming,” IEEE Conf. on Design Automation & Test in Europe, March 2010.

T. Moselhy, L. Daniel, “Variation-Aware Interconnect Extraction using Statistical Moment Preserving Model Order Reduction,” IEEE Conf. on Design Automation and Test in Europe (DATE), March 2010.  (Best Paper Award Nomination).

B. Bond, L. Daniel, “Model Order Reduction for Analog Integrated Circuits,” IEEE/ACM Design Automation Conference, Anaheim, CA, June 2010. (Invited Paper)

T. Moselhy, L. Daniel, “Stochastic Dominant Singular Vectors Method for Variation-Aware Extraction,” IEEE/ACM Design Automation Conf., Anaheim, CA, June 2010.

Y. Hsiao, T. Moselhy, L. Daniel, “FastCaplet: A Template-Based Capacitance Field Solver for 3D VLSI Interconnect,” 28th Progress in Electromagnetic Research Sympos., Cambridge, July 2010.

T. Moselhy, L. Daniel “Electromagnetic Simulation for Variation-Aware Interconnect Parasitic Extraction,” 28th Progress in Electromagnetics Research Symposium, Cambridge, MA, July 2010.

T. Moselhy, B. Bond, J. Lee, J. White, L. Daniel, “Stabilized Immerse Boundary Method for the Simulation of the Human Arterial System,” SIAM Conference on the Life Sciences, Pittsburgh, PA, July 2010. (Invited Paper)

B. Bond, T. Moselhy, L. Daniel, “System Identification Techniques for Modeling of the Human Arterial System,”  SIAM Conference on the Life Sciences, Pittsburgh, PA, July 2010. (Invited Paper)

B. Bond, Z. Mahmood, R. Sredojevic, Y. Li, A. Megretski, V. Stojanovic, Y. Avniel, L. Daniel, “Compact Stable Modeling of Nonlinear Analog Circuits using System Identification via Semi-Definite Programming and Robustness Certification,” IEEE Trans. on Computer Aided Design of Integrated Circuits and Systems, v.29,n.8, p.1149-1162, Aug. 2010.

Z. Mahmood, B. Bond, L. Daniel, “System Level Modeling and Simulation of Analog Circuits Using Semidefinite Programming Based Compact Modeling Techniques,” TECHCON 2010 conference, Austin, TX, 13-14 September 2010. (Best Paper in Session Award).

Z. Zhang, Q. Wang, N. Wong, L. Daniel, “A Moment-Matching Scheme for the Passivity-Preserving Model Order Reduction of Indefinite Descriptor Systems with Possible Polynomial Parts,” IEEE/ACM Asia Pacific Design Automation Conference, Yokohama, Japan, January 2011 (Best Paper Award Nomination).

L. Daniel, “Reduction Strategies for Linear and Nonlinear Electronic Systems,” Workshop on Reduction Strategies for the Simulation of Complex Problems, Milano, Italy, Jan 2011.

T. Moselhy, L. Daniel, “A Markov Chain Based Hierarchical Algorithm for Capacitance Extraction,” IEEE Trans. on Advanced Packaging, Special Issue Feb 2011. (Invited Paper)

T. Moselhy, L. Daniel, Invited Paper: “Variation-Aware Stochastic Extraction with Large Parameter Dimensionality: Review and Comparison of State of the Art Intrusive and Non-Intrusive Techniques,” International Symposium on Quality Electronic Design (IEQED), Santa Clara, CA March 2011.

Y. Hsiao, L. Daniel, “A Highly Scalable Parallel Boundary Element Method for Capacitance Extraction,” IEEE/ACM Design Automation Conf., San Diego, CA, June 2011.

L. Daniel, “New Advances and Future Directions in Model Reduction,” Workshop on Advances in Numerical Computation, Manchester UK, July 2011. (Invited Plenary)

Computational Electromagnetics Tools for High-field Magnetic Resonance Imaging

• Authors: Y. Zhao, A. Hochman, L. Wald, E. Adalsteinsson, L. Daniel
• Sponsorship: NIH

Two recent advances in Magnetic Resonance Imaging (MRI) technology have resulted in a need for sophisticated computational electromagnetics (CEM) tools. The first is the availability of higher magnetic fields, which can be used to improve signal-to-noise ratio. The second is the availability of transmit-coil arrays, which can be used to minimize human-body heating by electric fields. The higher magnetic fields imply higher-frequency RF pulses, which complicate electromagnetic analysis, as the dimensions of the human body and wavelength become comparable. They also imply increased human-body heating, which limits the RF power used for imaging purposes. In the Computational Prototyping Group, we are leveraging known CEM techniques to address these new needs of the MRI community, working in close collaboration with the RLE MRI group. Also, we are using the MRI application to drive the development of new CEM methods.

A number of MRI-based applications are being targeted. First, we are developing fast methods for tuning and matching the transmitters to the human-body loaded MRI coils. By using scattering-matrix formalism, a frequency-domain finite-elements method and commercial RF optimization software, we have shrunk this process from days to hours and are working to reduce it further by use of integral-equation methods. Second, we are developing a hybrid method-of-moments Green’s function approach that is tailored to the problem of optimizing the geometrical configuration of the transmit coils. In this method, we are pre-computing Green’s functions for a realistic model of the human body. Using these Green’s functions we hope to be able to rapidly assess different coil configurations for a typical body. To aid this assessment, we plan to leverage our work on parameterized model-order reduction, with which models of the parametric dependence of various quantities of interest can be generated automatically. Lastly, we are working on the problem of fast computation of approximate solutions to the electromagnetic fields inside the human body, assuming a simplified 3-tissue model that can be obtained for each patient by a quick MRI scan.



Figure 1: A scattering matrix formalism is used to generate a model for the transmit coils loaded by a human head. This model is then used in a commercial RF optimization package (RF Designer) to tune and match the coils to their drivers.



Figure 2: Electric fields generated by a 10-A current source about 5 cm away from the chest, obtained by the commercial HFSS package. Similar calculations are performed for such sources at points around the body. These fields yield a numerically calculated Green’s function for the human body, which can then be used in an integral-equation method to rapidly assess different coil configurations.




FastMarkov: A Markov Chain-based Hierarchical Solver for Large Scale Capacitance Extraction

• Authors: Y. Zhao, T. Moselhy, H. Fernandes R. Mathur, I. M. Elfadel, L. Daniel
• Sponsorship: SRC/FCRP IFC, AMD, Mentor Graphics



Figure 1: A sample layout containing 85 nets (represented by different colours) and 14 dielectric layers (removed from image for clarity). Image courtesy of Intel Corporation.

Standard full chip capacitance extraction algorithms rely for computational efficiency on 2D scanning and table lookup algorithms. These algorithms trade off accuracy for computational efficiency and result in significant error in the extracted capacitance of complex layouts. It is therefore desirable to use accurate field solvers for full chip extraction, which in general can be divided into two types: discretization-based and discretization-free. Discretization-based methods include the finite difference methods, finite element method, and boundary element method ^[1] , while the best-known discretization-free algorithms are the floating random walk method and its variants. It is widely accepted that discretization based methods are very efficient for small and medium-size structures and that discretization free methods are more efficient for very large structures. Recently, our group has proposed a Markov Chain-based hierarchical algorithm ^[2] to combine the advantages of both discretization-based and discretization-free methods.

In this project we further refine our algorithm and implement it in C++ for very large-scale capacitance extraction. A layout is first partitioned into smaller blocks, and the Markov Transition Matrix (MTM) for each block is computed. Then, the capacitance of the full layout is extracted by simulating the Markov Chain using random walk methods. Our algorithm is efficient because the computation of an MTM is derived from the capacitance matrix associated with each block. Such a matrix is computed using the Finite Difference Method, which can handle highly inhomogeneous structures including different dielectrics and metal fills. In addition, our algorithm does not require the assembly or the solution of any linear system of equations at the level of the full layout. Consequently, the algorithm requires very modest computational time and memory to compute the capacitance matrix of the full chip to field solver accuracy. In addition, our algorithm lends itself to efficient parallelization because both the computation of MTMs and the computation of random walks are embarrassingly parallelizable. The accuracy, efficiency, and almost linear scalability of the algorithm are being tested on FastMarkov – our C++ implemented, MPI-parallelized solver, which can handle large-scale, geometrically complex, industry provided examples (such as the one shown in Figure 1) in 45 min using 4-core parallelization. We have so far also verified that around 95% of computation time is spent on MTM computation, which can be reduced significantly by larger number parallelization.

1. K. Nabors and J. White, “Fastcap: a multipole accelerated 3-d capacitance extraction program,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 10, no. 11, pp. 1447-1459, Nov. 1991. [↩]
2. T. El-Moselhy, I. Elfadel, and L. Daniel, “A hierarchical floating random walk algorithm for fabric-aware 3d capacitance extraction,” in Proc. IEEE/ACM Int. Conf. Computer-Aided Design, 2009, page 752-758, San Jose CA. [↩]

Model Order Reduction of Fully Parameterized Systems by Recursive Least Square Optimization

• Authors: Z. Zhang, I. M. Elfadel, L. Daniel
• Sponsorship: MathWorks Fellowship

Parameterized model order reduction (PMOR) techniques can generate compact models reflecting the impact induced by design or process variations ^[1] in submicron digital, mixed-signal, and RF analog IC design. Such techniques have become highly desirable in the Electronic Design Automation (EDA) community in order to accelerate time-consuming design space explorations, sensitivity analysis, and automatic synthesis. In traditional PMOR algorithms, the input and output matrices are non-parameterized. Nevertheless, if we attempt to analyze the higher-order nonlinearity of parameterized analog/RF circuits, the input matrices of the resulting models may be parameterized. The input matrix can also be parameterized when the input signal is placed into a network after being processed by a parameter-dependent block (such as a MEMS sensor).

In this work, we are developing an MOR method for fully parameterized systems with variational input/output matrices. As proposed in ^[2] , this method generates some “optimal (block) vectors” by recursive least square (RLS) optimization to construct the projection matrix, through minimizing the error in the whole parameter space. By this error minimization procedure, much redundant information is eliminated and high accuracy can be guaranteed. Very small reduced-order models (ROM) can be obtained for multi-parameter models since the ROM size does not depend on parameter numbers. Since this algorithm is not based on small-perturbation analysis, it is applicable even when the parameter space is very large. Numerical results are presented for the four-port OTA-interconnect circuit in Figure 1, whose performance depends on the interconnect wire width (w) and spacing (l), as well as the chip temperature (T). Figure 2 gives the outputs of RLS-based PMOR algorithm for three circuit examples with different parameters, where significantly high accuracy is observed.



Figure 1: The four-port fully parameterized circuits for algorithm verification. OTAs 1-4 are four ideal operational trans-conductance amplifiers whose gains are dependent on T. The interconnect width (w) and spacing (l) are tunable. The w, l and T affect the parasitic effects of the metal buses. We attempt to find the transfer functions from the inputs u₁-u₄ to the outputs v_o1 – v_o4 at the far ends of the interconnects under different parameter values.



Figure 2: MOR results for Case 1 (w/w₀ = 3, l/l₀=1.5, T-T₀=10), Case 2 (w/w₀ = 15, l/l₀=7.5, T-T₀=50) and Case 3 (w/w₀ = 27, l/l₀=13.5, T-T₀=90­), with w₀, l₀ and T₀ being the nominal parameter values. (a) The transfer functions (from u₁ to v_o1) of the RLS-based reduced models (size=10) and the original ones (size=1004). (b) The maximum relative errors of the three cases are about 10^-5, 10^-6, and 10^-8, respectively.




1. L. Daniel, C. S. Ong, S. C. Low, K. H. Lee and J. White, “A multi-parameter moment matching model reduction approach for generating geometrically parameterized interconnect performance models,” IEEE Trans. Computer-Aided Design, vol. 23, no. 5, pp.678-693, May 2004. [↩]
2. Z. Zhang, I. M. Elfadel and L. Daniel, “Model order reduction of fully parameterized systems by recursive least square optimization,” Int’l. Conf. Computer Aided Design, San Jose, CA, Nov. 2011, submitted for publication. [↩]

Automated Passive Dynamical Model Extraction of Thin Film Bulk Acoustic Resonators (FBAR) for Time Domain Simulations

• Authors: Z. Mahmood, J. Lee, D. S. Boning, L. Daniel
• Sponsorship: SRC/FCRP IFC

Thin Film Bulk Acoustic Resonators (FBARs) are widely used in the design of modern radio frequency components including duplexers, filters, and oscillators. The overall goal of this project is to incorporate the performance parameters of these resonators into the design flow of the overall system. As a first step, the frequency response of the fabricated devices is measured. Traditionally, an equivalent circuit is then built based on least squares fitting of the frequency response of a simple RLC network to the measured data ^[1] . Such a technique is fairly simple, and the resulting equivalent model does capture important performance parameters, such as quality factor and resonant frequency. However, this technique cannot capture spurious resonances and other second order effects, which quite often play a significant role in the overall performance of the device.

In this work, we are developing tools that will automatically generate accurate, compact, and passive dynamical models for FBARs. Given measured transfer function samples, we identify a rational transfer function model that minimizes the mismatch at the given frequencies. These dynamical models can be interfaced with commercial circuit simulators for time domain simulations of a larger interconnected system. To guarantee the stability of the overall simulation, we ensure the passivity of our generated models by enforcing semidefinite constraints during the fitting process as proposed in ^[2] . Figure 1 shows the 3D layout of an FBAR. Numerical results are presented for resonators configured to constitute a bandpass frequency response. Figure 2 compares the output of our identified models with the given measured data.



Figure 1: (Courtesy of Coventor) 3D layout of FBAR.



Figure 2: Plot demonstrating the accuracy of our identified model. We compare measured Z parameters (green dots) with the output from our dynamical model (red solid lines). The plot is zoomed-in at the resonances. (Top: real part. Bottom: imaginary part.)




1. R. C. Ruby, P. Bradley, Y. Oshmyansky, A. Chien, and J.D. Larson, III, “Thin film bulk wave acoustic resonators (FBAR) for wireless applications,” Ultrasonics Symposium, 2001 IEEE, vol.1, no., pp. 813-821. [↩]
2. Z. Mahmood and L. Daniel, “Circuit synthesizable guaranteed passive modeling for multiport structures,”in Proc. Behavioral Modeling and Simulation Conference (BMAS), Sept. 2010. [↩]

Modeling and Simulation of Blood Flow in Arterial Networks

• Authors: Y.-C. Hsiao, P. Triverio, T. Moselhy, B. Bond, J. Lee, J. White, L. Daniel

Understanding certain medical conditions requires understanding specific aspects of the blood flow in the arterial network. For instance, diagnosing atherosclerosis requires capturing detailed flow inside an arterial segment. Such a study requires developing accurate solvers for the detailed equations describing both the blood flow and the elastic behavior of the arteries. On the opposite end of the spectrum, studying hypertension requires computing pressure and averaged flow over a larger arterial network. Such analysis requires developing compact computationally inexpensive models of complex segments of the arterial network. These models relate the pressure and average flow at the terminals of the arterial segments and must be easily interconnected to form complex and large arterial networks.

In this project we are developing a 2-D fluid-structure interaction solver to accurately simulate blood flow in arteries with bends and bifurcations. Such blood flow is mathematically modeled using the incompressible Navier-Stokes equations. The arterial wall is modeled using a linear elasticity model ^[1] . Our solver is based on an enhanced immersed boundary method (IBM) ^[2] . As a second step we are developing system identification techniques ^[3] to generate passive models for complex arterial segments such as large arteries, arterial bends, and bifurcations. We have validated our IBM solver results versus reference results obtained from MERCK Research Laboratories for a straight vessel of 10-cm length and 2-cm diameter. Our results for pressure, flow, and radius variations are within 3% of those obtained from MERCK. Furthermore, we are validating our model results by cascading different models and comparing the results of the resulting network to those predicted by the IBM solver. Our preliminary results for pressure and flow at the terminals of the models are within 10% of those obtained from the full simulator. In addition, by using the models we obtain a more than 100,000 times reduction in the computational time.



Figure 1: We use i) our immersed boundary method for incompressible Navier-Stokes to extract a complete model and ii) our system identification technique to construct a reduced model ^[3] . The lower part shows three major artery geometries we use for modeling a cardiovascular system.



Figure 2: A 20-cm artery is constructed by cascading two 10-cm artery models terminated with a matched load. The transient simulation results of the cascaded model are compared with those of a 20-cm artery solved by our immersed boundary method solver.




1. A. Quarteroni, M. Tuveri, and A. Veneziani, “Computational vascular fluid dynamics: problems, models and methods,” Computing and Visualization in Science, vol. 2, no. 4, pp. 163-197, Mar. 2000. [↩]
2. C. Peskin and D. McQueen, “A three-dimensional computational method for blood flow in the heart I. Immersed elastic fibers in a viscous incompressible fluid,” Journal of Computational Physics, vol. 81, no. 2, pp. 372-405, Apr. 1989. [↩]
3. B. Bond, T. Moselhy, and L. Daniel, “System identification techniques for modeling of the human arterial system,” Proc. SIAM Conference on the Life Sciences, July 2010, pp. 12-15. (Invited Paper) [↩] [↩]

A Highly Scalable Parallel Boundary Element Method for Capacitance Extraction

• Authors: Y.-C. Hsiao, L. Daniel
• Sponsorship: SRC/FCRP IFC, SRC/FCRP GRC, Mentor Graphics, AMD

Standard boundary element methods (BEMs) involve both an embarrassingly parallelizable system setup step and a linear system solving step of time complexity O(N³) that cannot be parallelized efficiently. When piecewise constant (PWC) basis functions are adopted to represent solutions, the system solving step dominates the overall computation time (usually more than 90%) and limits the scalability of standard BEMs with the number of parallel computing nodes. For capacitance extraction problems, traditional acceleration techniques, such as the multipole expansion ^[1] and the pre-corrected FFT methods ^[2] , can reduce the solving time complexity to O(N log N). However, available parallelization implementations of these two techniques showed that their parallel acceleration saturates quickly with the number of parallel nodes: their parallel efficiency drops to 40% to 60% at just 8 nodes ^{[3] [4]} .

The aforementioned methods suffer from poor parallel scalability because their underlying solution representation, PWC basis functions, is inefficient for representing charge distribution, resulting in a large linear system. Solving such a large system dominates the overall computation and drastically degrades the parallel efficiency. To circumvent the bottleneck of solving a large system in parallel, we employ our recently developed instantiable basis functions, which are 30 times more compact than PWC basis functions for the same capacitance accuracy ^[5] . Accordingly, the computation for solving a system is reduced from the original 90% of the total time to less than 5%, while the embarrassingly parallelizable part is now dominant (growing from 10% of the total time to more than 95%). In addition, we develop four integration techniques to further accelerate the system matrix filling process by 86%. In our demonstrated examples, our new algorithm is 6 times faster than FastCap ^[1] in a single-core environment and achieves 90% parallel efficiency on a 2-cpu-10-core distributed memory system implemented in C++ with MPI parallelization ^[6] .



Figure 1: The charge distribution solutions represented by (a) 572 PWC basis functions and (b) 17 instantiable basis functions, respectively. The capacitance errors for both cases are 2% with respect to a reference capacitance value extracted by the standard BEM with fine discretization.



Figure 2: (a) An industry provided interconnect example. Our integration techniques accelerate by 86%. The overall algorithm is 6 times faster than FastCap ^[1] for single-threaded execution at the same accuracy (a 2.8% error w.r.t. a reference value). (b) A 24×24 bus example and its parallel efficiency comparison in (c) with the algorithms in ^[3] and ^[4] .




1. K. Nabors and J. White, “FastCap: A multipole accelerated 3-D capacitance extraction program,” IEEE Transactions on Computer-Aided Design, vol. 10, no. 10, pp. 1447-1459, Nov. 1991. [↩] [↩] [↩]
2. J. R. Phillips and J. K. White, “A precorrected-FFT method for electrostatic analysis of complicated 3-D structures,” IEEE Transaction on Computer-Aided Design, vol. 16, no. 10, pp. 059-1072, Oct. 1997. [↩]
3. Y. Yuan and P. Banerjee, “A parallel implementation of a fast multipole-based 3-d capacitance extraction program on distributed memory multicomputers,” Journal of Parallel and Distributed Computing, vol. 61, no. 12, pp. 1751–1774, Dec. 2001. [↩] [↩]
4. N. R. Aluru, V. B. Nadkarni, and J. White, “A parallel precorrected FFT based capacitance extraction program for signal integrity analysis,” Proc. 33^rd annual Design Automation Conference, 1996, pp. 363–366. [↩] [↩]
5. Y.-C. Hsiao, T. El-Moselhy, and L. Daniel, “Efficient capacitance solver for 3d interconnect based on template-instantiated basis functions,” IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems, 2009, pp. 179–182. [↩]
6. Y.-C. Hsiao and L. Daniel, “A highly scalable parallel boundary element method for capacitance extraction,” Proc. 48^th Annual Design Automation Conference, 2011, pp. 552–557. [↩]

Compact Modeling of NON-LINEAR Analog Circuits Using System Identification via Semidefinite Programming and Incremental Stability Certification

• Authors: B. Bond, Z. Mahmood, A. Megretski, L. Daniel
• Sponsorship: DARPA, SRC/FCRP IFC

During recent years, researchers of the Electronic Design Automation community have made a great effort to develop new techniques for automatically generating accurate compact models of NON-LINEAR system blocks. The majority of the existing methods for creating stable reduced models of nonlinear systems, such as ^[1] , require knowledge of the internal structure of the system, as well as access to the exact model formulation for the original system.  Unfortunately, this information may not be easily available if a designer is using a commercial design tool, or may not even exist if the system to be modeled is a physical fabricated device.

As an alternative approach to nonlinear model reduction, we have proposed a system-identification procedure.  This procedure requires only data available from simulation or measurement of the original system, such as input-output data pairs.  By enforcing incremental stability, as shown in ^[2] , it is possible to formulate a semi-definite optimization problem whose solution is a stable nonlinear model that optimally matches the given data pairs from the original system.  In addition, the proposed optimization formulation, explained in detail in ^[3] , allows users to specify completely the complexity of the identified reduced model through the choice of both model order and nonlinear function complexity.

Applications for the proposed modeling technique include analog circuit building blocks such as operational amplifiers and power amplifiers, MEMS devices, and individual circuit elements such as transistors.  The resulting compact models may then be used in a higher-level design optimization process of a larger system.   One such example of an analog circuit block is the low-noise amplifier shown in Figure 1; it contains both nonlinear and parasitic elements.  For this example, input-output training data was generated from a commercial circuit-simulator and used to identify a compact nonlinear model.  The output responses of the original system and the identified model are compared in Figure 2.



Figure 1: Application example: Low-noise amplifier designed in CMOS technology.



Figure 2: Time domain outputs, over a small portion of the period, of the original LNA circuit from a commercial circuit simulator (solid line) and the stable nonlinear compact model identified by our procedure (dots) in response to an input signal different from the training signals.




1. B. Bond and L. Daniel, “Stabilizing schemes for piecewise-linear reduced order models via projection and weighting functions,” in Proc. IEEE Conference on Computer-Aided Design, San Jose, CA, Nov. 2007, pp. 860-867. [↩]
2. A. Megretski, “Convex optimization in robust identification of nonlinear feedback,” in Proc. IEEE Conference on Decision and Control, Cancun, Mexico, Dec. 2008, pp. 1370-1374. [↩]
3. B. Bond, Z. Mahmood, Y. Li, R. Sredojevic, A. Megretski, V. Stojanovic, Y. Avniel, and L. Daniel, “Compact Modeling of Nonlinear Analog Circuits Using System Identification via Semidefinite Programming and Incremental Stability Certification,” Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on , vol.29, no.8, pp.1149-1162, Aug. 2010. [↩]

Circuit Simulation Using a Verilog-A Implementation of the Virtual-source Transistor Model

• Authors: O. Mysore, D. A. Antoniadis, L. Daniel
• Sponsorship: SRC/FCRP MSD

A variety of compact MOSFET models are used for circuit simulation in both industry and academia, ranging from standard industrial models with dimensional and processing parameter dependencies ^[1] to simple, intuitive physical transport models. The virtual-source model (VS model), a recently developed, simple, semi-empirical, short channel MOSFET model, captures the essential physics with relatively few physical parameters, most of which can be directly determined from device measurements or simulations ^[2] .  Because of its accuracy, simplicity, and scalability, the VS model is excellent for technology benchmarking, performance projection and variability analysis.



Figure 1: Waveform of ring oscillator node voltages.

Previous work on this project involved the implementation of the VS model, including intrinsic charges, in a commercial simulator using Verilog-A, an analog descriptive language.  Commercial circuit simulators allow users to create Verilog-A behavioral modules, which specify the relationships between currents and voltages of the internal and external nodes of the module.  Using such a module, the VS model, including intrinsic charges, was implemented in Verilog-A.  This project uses the Verilog-A implementation of the model to simulate a number of circuits.

Circuits such as ring oscillators, adders, and FIR-filters were simulated in commercial simulators using the Verilog-A implementation of the VS model.  Ring oscillators ranging from fan-out one to seven were implemented, and the delays were compared to experimental data from fabricated ring oscillators.  For the ring oscillators, the appropriate VS model parameters were extracted from measured data, and the parameters were varied in simulations in order to obtain sensitivity analyses.  The node voltages of a fivestage ring oscillator are shown in Figure 1.  For larger circuits, such as an FIR-filter, when convergence difficulties arose, smoothing functions substantially improve convergence.  Based on the circuits implemented as part of this project, using Verilog-A modules in commercial simulators is an adequate method of simulating circuits with the VS model.

1. C. Hu. “BSIM.” Internet: http://www-device.eecs.berkeley.edu/~bsim3/bsim4.html [June 31, 2009]. [↩]
2. A. Khakifirooz, “A simple semiempirical short-channel MOSFET current-voltage model continuous across all regions of operation and employing only physical parameters,” IEEE Transactions on Electron Devices, vol. 56, pp. 1674-1680, 2009. [↩]