MTL Annual Report

Collaborators

• E. Alon, UC Berkeley
• K. Asanovic, UC Berkeley
• T.-J. King Liu, UC Berkeley
• A. Kavcic, U. Hawaii at Manoa
• D. Markovic, UC Los Angeles
• C-K. K. Yang, UC Los Angeles

Graduate Students

• W. An, EECS
• F. Chen, Research Assistant, EECS
• H. Fariborzi, Research Assistant, EECS
• M. Georgas, Research Assistant, EECS
• J. Leu, Research Assistant, EECS
• Y. Li, Research Assistant, EECS
• B. Moss, Research Assistant, EECS
• S. Song, Research Assistant, EESC
• R. Sredojević, Research Assistant, EECS
• C. Sun, Research Assistant, EECS
• O. Uyar, Research Assistant, EECS

Publications

C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. Holzwarth, M. Popovic, H. Li, H. Smith, J. Hoyt, F. Kaertner, R. Ram, V. Stojanović, and K. Asanovic, “Building manycore processor to DRAM networks with monolithic CMOS silicon photonics [Invited],” IEEE Micro, vol. 29, no. 4, pp. 8-21, 2009.

N. Blitvic, M. Lee, and V. Stojanović, “Channel Coding for High-speed Links: A systematic look at code performance and system simulation [Invited],” IEEE Transactions on Advanced Packaging, vol. 2, no. 32, pp. 268-279, 2009.

K.S. Oh, F. Lambrecht, S. Chang, Q. Lin, J. Ren, C. Yuan, J. Zerbe, and V. Stojanović, “Accurate System Voltage and Timing Margin Simulation in High-Speed I/O System Design,” IEEE Transactions on Advanced Packaging, vol. 31, no. 4, pp. 722-730, 2008.

B. Kim and V. Stojanović, “Modeling and Design Framework: Equalized and Repeated Interconnects for Networks-on-Chip [Invited],” IEEE Design & Test of Computers, vol. 25, no. 5, pp. 430-439, 2008.

T. Barwicz, H. Byun, F. Gan, C. W. Holzwarth, M. A. Popovic, P. T. Rakich, M. R. Watts, E. P. Ippen, F. X. Kärtner, H. I. Smith, J. S. Orcutt, R. J. Ram, V. Stojanovic, O. O. Olubuyide, J. L. Hoyt, S. Spector, M. Geis, M. Grein, T. Lyszczarz, and J. U. Yoon, ” Silicon photonics for compact, energy-efficient interconnects [Invited],” J. Opt. Netw. 6, 63-73 (2007)

F. Chen, M. Spencer, R. Nathanael, C. Wang, H. Fariborzi, A. Gupta, H. Kam, V. Pott, J. Jeon, T-J. K. Liu, D. Marković, V. Stojanović, and E. Alon, “Demonstration of Integrated Micro-Electro-Mechanical (MEM) Switch Circuits for VLSI Applications,” IEEE International Solid-State Circuits Conference, San Francisco, CA, pp. 150-151, February 2010.

J. S. Orcutt, A. Khilo, M. A. Popović, C. W. Holzwarth, H. Li, J. Sun, B. Moss, M. S. Dahlem, E. P. Ippen, J. L. Hoyt, V. Stojanović, F. X. Kartner, H. I. Smith, R. J. Ram, “Photonic integration in a commercial scaled bulk-CMOS process,” IEEE International Conference on Photonics in Switching, Pisa, Italy, pp. 1-2, September 2009.

F. Chen, A. Chandrakasan, and V. Stojanović, “An Oscilloscope Array for High-Impedance Device Characterization,” European Solid-State Circuits Conference, Athens, Greece, 4 pages, September 2009.

A. Joshi, B. Kim, and V. Stojanović,”Designing Energy-efficient Low-diameter On-chip Networks with Equalized Interconnects,” IEEE Symposium on High-Performance Interconnects, New York, NY, 10 pages, August 2009.

Y. Li and V. Stojanović, “Yield-driven Iterative Robust Circuit Optimization Algorithm,” ACM/IEEE Design Automation Conference, San Francisco, CA, 6 pages, July 2009.

S.Song, B. Kim, and V. Stojanović, “A Fractionally Spaced Linear Receive Equalizer with Voltage-to-Time Conversion,” IEEE Symposium on VLSI Circuits, Kyoto, Japan, pp. 222-223, June 2009.

A. Joshi, C. Batten, Y-J. Kwon, S. Beamer, K. Asanović, and V. Stojanović, “Silicon-Photonic Clos Networks for Global On-Chip Communication,” 3rd ACM/IEEE International Symposium on Networks-on-Chip, San Diego, CA, pp. 124-133, May 2009.

B. Kim and V. Stojanović, “A 4 Gb/s/ch 356fJ/b 10 mm Equalized On-Chip Interconnect with Nonlinear Charge-Injecting Transmit Filter and Transimpedance Receiver in 90 nm CMOS Technology,” IEEE International Solid-State Circuits Conference, San Francisco, CA, pp. 66-67, February 2009.

R. Sredojević and V. Stojanović, “Optimization-based Framework for Simultaneous Circuit and System Design-Space Exploration: A High-Speed Link Example,” IEEE/ACM International Conference on Computer-Aided Design, San Jose, CA, pp. 314-321, November 2008.

F. Chen, H. Kam, D. Marković, T.J. King, V. Stojanović, and E. Alon, “Integrated Circuit Design with NEM Relays,” IEEE/ACM  International Conference on Computer-Aided Design, San Jose, CA, pp. 750-757, November 2008.