MTL Annual Report

In this work, we are designing high-performance pipeline ADCs using the zero-crossing-based structure ^[1] , which is an extension of the comparator-based switch-capacitor circuit (CBSC) design methodology ^[2] . The focus of the project is to explore novel circuit structures based on zero-crossing detection to improve the FOM of zero-crossing-based circuits (ZCBC). In particular, we are investigating the use of a differential structure to improve ZCBC’s robustness against common mode noise. An additional benefit of differential design is the increase in the available signal range, which helps to improve SNR. We implemented a multi-bit MDAC to improve its power efficiency and to help relax component accuracy requirements. In this design, we used the Decision Boundary Gap Estimation to digitally correct for capacitor mismatch ^[3].  The ADC achieves an ENOB of 10.2 at 100MS/s while consuming 6.2 mW.

In another iteration of this project, time-interleaving is used to achieve ultra-high sampling rates with very low power. In a time-interleaved structure, matching between the different channels will be very important to maintain the desired performance. Any mismatch in non-idealities such as gain error, offset, and timing errors can greatly degrade the performance. We use a skew correction circuit to remove the timing-skew. Careful design and layout are needed to reduce the other mismatches.

1. L. Brooks, H.-S. Lee, “A zero-crossing-based 8b 200MS/s pipelined ADC,” IEEE Int’l Solid-State Circuits Conf. Dig. of Tech. Papers, ISSCC, 2007, pp.15-17. [↩]
2. T. Sepke, J.K. Fiorenza, C.G. Sodini, P. Holloway and H.-S. Lee, “Comparator-based switched-capacitor circuits for scaled CMOS technologies,” IEEE Int’l Solid-State Circuits Conf. Dig. of Tech. Papers, ISSCC, 2006, pp. 220-221. [↩]
3. L. Brooks and H.-S. Lee, “Background calibration of Pipelined ADCs via Decision Boundary Gap Estimation,“ IEEE Trans. Circuits and Systems I, Nov. 2008 [↩]