MTL Annual Research Report 2012

Time-interleaved A/D Converters

There is an ever-increasing demand for high-resolution and high-accuracy A/D converters in communication systems. In order to raise the sampling rates to the GHz range in a power efficient manner, time-interleaving is an essential technique whereby N A/D channels each operating at a sampling frequency f_s are used to achieve an effective conversion speed of Nf_s as illustrated in Figure 1.

While time-interleaving enables higher conversion rates in a given technology, mismatch issues such as gain, offset, and sampling clock skew errors between channels degrade the overall A/D performance ^[1] . Of these issues, sampling clock skew between channels is the biggest problem in time-interleaved A/Ds with high resolution and high sampling rates. There are a few sources of sampling clock skew between channels. Mismatches in the sampling clock path and logic delays are the most obvious. Input signal routing mismatch and RC mismatch of the input sampling circuits also cause sampling clock skew. The sampling skew can be mitigated by various calibration techniques. Previous calibration techniques employ either analog and digital timing adjustment or digital calibration of output data. The timing adjustment requires adjustable delay resulting in increased sampling jitter, which cannot be compensated by calibration. The digital calibration of output data requires complex interpolation.

In this research project, we are developing a much simpler calibration algorithm for sampling clock skew based on rapid consecutive sampling whereby two samples of the input are acquired a short time apart for each A/D channel. The consecutive sampling method allows for a simple linear interpolation, and the impact on noise or power consumption in the analog circuits is negligible. Since the calibration algorithm is simple, the power consumption in the digital calibration circuits will be low. We are implementing a 12b, 1GS/s time-interleaved ADC to demonstrate the new calibration scheme.

Figure 1: Block diagram of a time-interleaved (TI) A/D.

1. N. Kurosawa, H. Kobayashi, K. Maruyama, H. Sugawara, and K. Kobayashi, “Explicit analysis of channel mismatch effects in time-interleaved ADC systems,” IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 48, no. 3, pp. 261-271, Mar. 2001. [↩]