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Download as PDFFabrication of Si Nanowire-based Capacitors for Power Management
Capacitors with high capacitance density (capacitance per footprint area) have potential applications in autonomous microsystems and for power management in high performance integrated circuits. For self-powered autonomous systems, batteries are needed for storage of harvested energy with high energy densities. However, batteries are limited in their discharge power. Coupled with capacitors, stored energy can be released at high powers, e.g., for broadcast of data. Supercapacitors can also be used in on-chip switched capacitor converters for dynamic voltage scaling in low power integrated circuits [1] .
We are investigating the use of silicon nanowire arrays for fabrication of on-chip supercapacitors. To fabricate nanowire arrays, we are using metal catalyzed etching (MCE) (Figure 1). This is a room temperature wet etching process that has been used to create arrays of nanowires with radii and spacing in the range of tens of nanometers, with wire aspect ratios of over 200 to 1 [2] .
In earlier work, we demonstrated the feasibility of using the MCE to fabricate Si nanowires to make supercapacitors (Figure 2) [3] . We have demonstrated a factor of approximately 10 times improvement in the capacitance density over planar devices for nanocapacitors with a 200-nm period and 1.5-μm height. Further improvement of silicon nanowire capacitors can be achieved by optimizing the geometries of the nanowire arrays and the dielectric material and structure, as well as the device layout. Our current work has focused on improving the capacitor performance by decreasing the equivalent series resistance. Lower resistance will provide a higher AC effective capacitance density and less heat generation. Two approaches are under investigation to reduce the series resistance. One is through improved design of nanocapacitor arrays; the other is conversion silicon nanowires to silicide nanowires.
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- Figure 1: Scheme of the MCE process.
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- Figure 2: Schematic nanocapacitor process flow.
- Y. K. Ramadass and A. P. Chandrakasan, “Voltage scalable switched capacitor DC-DC converter for ultra-low-power on-chip applications,” in IEEE Power Electronics Specialists Conference, 2007, pp. 2353-2359. [↩]
- S. W. Chang, V. P. Chuang, S. T. Boles, C. A. Ross, and C. V. Thompson, “Densely-packed- arrays of ultrahigh-aspect-ratio silicon nanowire fabricated using block copolymer lithography and metal-assisted etching,” Advanced Functional Materials, vol. 19, p. 2495, 2009(5). [↩]
- S. W. Chang, J. Oh, S. T. Boles, and C. V. Thompson, “Fabrication of silicon nanopillar-based nanocapacitor arrays,” Applied Physics Letters, vol. 96, p. 153108, 2010(4). [↩]