Self-aligned Sub-100-nm InGaAs MOSFETs for Logic Applications
- Category: Electronic Devices
- Tags: dimitri antoniadis, jesús del alamo, mosfets
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Download as PDFInGaAs-based metal-oxide-semiconductor field-effect transistors (MOSFETs) have shown great potential for future high- performance and low-power logic applications [1] . Superior electron transport properties [2] and impressive device prototypes have been recently demonstrated [3] [4] . The parasitic resistance is an important problem to address, especially in deeply scaled devices. In addition, the gate-contact separation has to be kept to a minimum to achieve the device footprint goals. We address these requirements by introducing a novel transistor architecture with self-aligned contacts and a gate-last fabrication scheme.
In this work, self-aligned InGaAs quantum-well MOSFETs in the sub-100-nm regime have been demonstrated. A cross- sectional SEM image of a device with gate length of 90 nm is shown in Figure 1. As shown, the S/D metal (Mo) and the n+ cap are self-aligned to the gate. With an optimized recess etch process, the device has achieved a very tight S/D-to-channel spacing (Lside < 20 nm). The channel consists of an InGaAs quantum well buried under a thin InP layer. A composite dielectric consisting of thin layers of Al2O3 and HfO2 is grown by atomic layer deposition (ALD). Well-behaved output characteristics are shown in Figure 2 for a 90-nm-gate length device. The total on-resistance of this device at Vgs-Vt= 0.7 V is 595 W.mm which is an excellent value. The subthreshold swing for a 60-nm-gate device at Vds = 0.5 V is 120 mV/dec. The gate current is below 3×10-3 A/cm2 at the maximum operating voltage (Vgs-Vt =0.7 V). The process yields devices with gate lengths down to 30 nm with acceptable parasitic resistance. This self-aligned architecture will enable us to explore the scaling behavior and electron transport characteristics of InGaAs QW-MOSFETs in a dimensional range of interest for future CMOS.
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- Figure 1: SEM cross-section of a QW-MOSFET with 90-nm gate length and very tight S/D-to gate spacing.
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- Figure 2: Output characteristics of a QW-MOSFET with 90-nm gate length.
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