Duane S. Boning

  • Title: Professor
  • Department: Department of Electrical Engineering and Computer Science

Collaborators

  • A. Elfadel, Masdar Institute
  • A. Philipossian, Univ. of Arizona
  • H. Taylor, NTU, Singapore

Graduate Students

  • K. Balakrishnan, Res. Asst., EECS
  • A. Chang, Res. Asst., EECS
  • W. Fan, Res. Asst., EECS
  • C. GoGwilt, Res. Asst., EECS
  • J. Lee, Res. Asst., EECS
  • J. Johnson, Res. Asst., EECS
  • L. Yu, Res. Asst., EECS

Support Staff

  • G. Lindsay, Admin. Asst. II
  • M. Whiting, Admin. Asst. II

Publications

N. Drego,  A. Chandrakasan, D. Boning, and D. Shah, “Reduction of Variation-Induced Energy Overhead in Multi-core Processors,” IEEE Transactions on Computer-Aided Design, vol. 30, no. 6, pp. 891-904, June 2011.

H. Taylor, K. Smistrup, and D. Boning, “Modeling and simulation of stamp deflections in nanoimprint lithography: exploiting backside grooves to enhance residual layer thickness uniformity,” Microelectronic Engineering, vol. 88, no. 8, pp. 2154-2157, August 2011.

H. Taylor, D. Boning, and C. Iliescu, “A razor-blade test of the demolding energy in a thermoplastic embossing process,” Journal of Micromechanics and Microengineering, vol. 21, no. 6, p. 067002, June  2011.

R. K. Jena, H. K. Taylor, Y. C. Lam, D. S. Boning, and C. Y. Yue, “Effect of polymer orientation on pattern replication in a micro-hot embossing process: experiments and numerical simulation,” Journal of Micromechanics and Microengineering, vol. 21, no. 6, p. 065007, June  2011.

A. H. Chang, D. Boning, and H.-S. Lee, “Redundancy in SAR ADCs,” Great Lakes Symposium on Very Large Scale Integration (GLSVLSI), Lausanne, Switzerland, May 2011.

K. Balakrishnan, K. A. Jenkins, and D. Boning, “A Ring Oscillator-Based Test Structure for AC Variability Characterization of Individual MOSFETs,” 2nd European Workshop on CMOS Variability (VARI), 4 pages, Grenoble, France, May 2011.

W. Y. Zhang, X. Li, R. Rutenbar, K. Balakrishnan, and D. Boning, “Toward Efficient Spatial Variation Decomposition via Sparse Regression,” IEEE International Conference on Computer-Aided Design (ICCAD), Nov. 2011.

W. Fan, D. Boning, Y. Zhuang, Y. Sampurno, A. Philipossian, M. Moinpour and D. Hooper, “Characterization of CMP Pad Surface Properties and Aging Effects,” International Conference on Planarization Technology (ICPT), Seoul, Korea, Nov. 2011.

J. Johnson, D. Boning, G.-S. Kim, R. Mudhivarthi, P. Safier, and K. Pate, “Slurry Particle Agglomeration Model for Chemical Mechanical Planarization (CMP),” International Conference on Planarization Technology (ICPT), Seoul, Korea, Nov. 2011.

A. H. Chang, K. Zuo, J. Wang, D. Yu, and D. Boning, “Test Structure, Circuits and Extraction Methods to Determine the Radius of Influence of STI and Polysilicon Pattern Density,” IEEE International Symposium on Quality Electronic Design (ISQED), March 2012.

L. Yu, W.-Y. Chang, K. Zuo, J. Wang, D. Yu, and D. Boning, “Methodology for Analysis of TSV Stress Induced Transistor Variation and Circuit Performance,” IEEE International Symposium on Quality Electronic Design (ISQED), March 2012.

W. Zhang, K. Balakrishnan, X. Li, D. Boning, E. Acar, F. Liu, and R. A. Rutenbar, “Spatial Variation Decomposition via Sparse Regression,” International Conference on IC Design and Technology (ICICDT), Austin, TX, May 2012.

Faculty & Topics