A Monolithic Electronic-photonic Integration Platform in Commercial 45-nm SOI

  • Authors: B. R. Moss, C. Sun, M. Georgas, J. Leu, J. Orcutt, J. Shainline, K. Mehta, J. Sun, H. Li, E. Timurdogan, S. Urosevic, E. Zgraggen, M. Weaver, M. Popovic, R. Ram, M. Watts, V. Stojanović
  • Sponsorship: CICS, DARPA, NSF, SRC/FCRP IFC, Trusted Foundry, Intel, NSERC

Integrated photonic interconnects present a disruptive alternative to electrical I/O for many VLSI applications, with potential for superior bandwidth density through dense-wavelength-division-multiplexing (DWDM) and energy-efficient operation through both monolithic integration and lower transmission losses. There are two main paths toward an integrated platform. Hybrid designs [1] [2] [3] enable each component to be custom-tailored but penalize energy efficiency due to large parasitic and packaging capacitance. Manufacturing costs can also increase due to requisite process flows and costly 3D integration or microbump packaging. Monolithic integration offers reduced power and cost but has not penetrated deeply scaled technologies due to necessary process customizations. The platform in Figure 1 monolithically integrates all necessary photonic components (vertical grating couplers, ring filters, modulators, and photodiodes) with electronics in a commercial state-of-the-art 45-nm SOI process with no foundry changes. High-speed electrical and optical components are placed with micron-scale proximity on the same die, minimizing interface parasitics without sacrificing performance or commercial scalability. The eye diagram represents the first fully monolithic electro-optic modulation in 45-nm technology, driven by an on-chip double-data-rate modulator driver. The driver is a configurable all-digital push-pull circuit with sub-bit-time pre-emphasis and split supplies. Due to long carrier lifetimes in silicon and relatively long intrinsic region of these particular modulator designs, the rate is limited to 600Mb/s, achievable in both 1280-nm and 1550-nm bands.  Further device design and biasing optimization will improve performance into the multi-Gb/s range. Figure 2 shows an 8-ring filter bank with 30-GHz bandwidth wavelength-channels fabricated in order and distributed across a 2.04-THz free spectral range. Integrated sigma-delta heater drivers thermally tune rings to a 250-GHz grid with an efficiency of 2.6mW/nm, compensating for ring-resonance mismatch due to process variation and enabling high bandwidth density through DWDM.

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