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Download as PDFModel Order Reduction of Fully Parameterized Systems by Recursive Least Square Optimization
Parameterized model order reduction (PMOR) techniques can generate compact models reflecting the impact induced by design or process variations [1] in submicron digital, mixed-signal, and RF analog IC design. Such techniques have become highly desirable in the Electronic Design Automation (EDA) community in order to accelerate time-consuming design space explorations, sensitivity analysis, and automatic synthesis. In traditional PMOR algorithms, the input and output matrices are non-parameterized. Nevertheless, if we attempt to analyze the higher-order nonlinearity of parameterized analog/RF circuits, the input matrices of the resulting models may be parameterized. The input matrix can also be parameterized when the input signal is placed into a network after being processed by a parameter-dependent block (such as a MEMS sensor).
In this work, we are developing an MOR method for fully parameterized systems with variational input/output matrices. As proposed in [2] , this method generates some “optimal (block) vectors” by recursive least square (RLS) optimization to construct the projection matrix, through minimizing the error in the whole parameter space. By this error minimization procedure, much redundant information is eliminated and high accuracy can be guaranteed. Very small reduced-order models (ROM) can be obtained for multi-parameter models since the ROM size does not depend on parameter numbers. Since this algorithm is not based on small-perturbation analysis, it is applicable even when the parameter space is very large. Numerical results are presented for the four-port OTA-interconnect circuit in Figure 1, whose performance depends on the interconnect wire width (w) and spacing (l), as well as the chip temperature (T). Figure 2 gives the outputs of RLS-based PMOR algorithm for three circuit examples with different parameters, where significantly high accuracy is observed.
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- Figure 1: The four-port fully parameterized circuits for algorithm verification. OTAs 1-4 are four ideal operational trans-conductance amplifiers whose gains are dependent on T. The interconnect width (w) and spacing (l) are tunable. The w, l and T affect the parasitic effects of the metal buses. We attempt to find the transfer functions from the inputs u1-u4 to the outputs vo1 – vo4 at the far ends of the interconnects under different parameter values.
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- Figure 2: MOR results for Case 1 (w/w0 = 3, l/l0=1.5, T-T0=10), Case 2 (w/w0 = 15, l/l0=7.5, T-T0=50) and Case 3 (w/w0 = 27, l/l0=13.5, T-T0=90), with w0, l0 and T0 being the nominal parameter values. (a) The transfer functions (from u1 to vo1) of the RLS-based reduced models (size=10) and the original ones (size=1004). (b) The maximum relative errors of the three cases are about 10-5, 10-6, and 10-8, respectively.
- L. Daniel, C. S. Ong, S. C. Low, K. H. Lee and J. White, “A multi-parameter moment matching model reduction approach for generating geometrically parameterized interconnect performance models,” IEEE Trans. Computer-Aided Design, vol. 23, no. 5, pp.678-693, May 2004. [↩]
- Z. Zhang, I. M. Elfadel and L. Daniel, “Model order reduction of fully parameterized systems by recursive least square optimization,” Int’l. Conf. Computer Aided Design, San Jose, CA, Nov. 2011, submitted for publication. [↩]