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Download as PDFA High-accuracy, Zero-crossing-based Pipeline ADC
Technology scaling poses challenges in designing analog circuits because of the decrease in intrinsic gain and reduced swing. An alternative to using high-gain amplifiers in the implementation of switched capacitor circuits has been proposed [1] that replaces the amplifier with a current source and a comparator. The new comparator-based switch capacitor (CBSC) and zero-crossing-based circuit (ZCBC) techniques have been implemented in two pipelined ADC architectures at 10 MHz and 200 MHz and 10-bit and 8-bit accuracy, respectively [1] [2] .
The purpose of this project is to explore the use of the ZCBC technique for very-high-precision AD converters. The goal of the project is a 100 MHz, 14-bit pipelined ADC. First, we are investigating dual-phase hybrid ZCBC operation to improve the power-linearity tradeoff of the A/D conversion [3] and to improve the power supply rejection. The first phase approximates the final output value, while the second phase allows the output to settle to its accurate value. Since the output is allowed to settle in the second phase, the currents through capacitors decay, permitting higher accuracy and power-supply rejection compared with standard ZCBCs. We are also developing linearization techniques for the ramp waveforms. Linear ramp waveforms require less correction in the second phase for given linearity, thus allowing faster operation. Innovative techniques for improving linearity beyond using a cascoded current source are explored; these techniques include output pre-sampling and bi-directional output operation. In addition, overshoot reduction calibration is implemented to improve the linearity requirements of the final phase. Digital self- calibration will be explored to reduce the residual constant offset. The ADC was implemented in a 65-nm 1-V process, and its operation is currently being evaluated.
- T. Sepke, J. K. Fiorenza, C. G. Sodini, P. Holloway, and H.-S. Lee, “Comparator-based switched capacitor circuits for scaled CMOS technologies,” IEEE International Solid State Circuits Conference Digest of Technical Papers, Feb. 2006, pp. 220-221. [↩] [↩]
- L. Brooks and H.-S. Lee, “A zero-crossing based 8b 200MS/s pipelined ADC,” IEEE International Solid State Circuits Conference Digest of Technical Papers, Feb. 2007, pp. 460-461. [↩]
- J. K. Fiorenza, “A comparator-based switched –capacitor pipelined analog-to-digital converter,” Ph.D. thesis, Massachusetts Institute of Technology, Cambridge, 2007. [↩]