All entries for Marcus Yip

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A Low-Voltage Digitally-Assisted Analog Front-End IC for a Wearable ECG Monitor

• Authors: M. Yip, A. P. Chandrakasan
• Sponsorship: Texas Instruments, NSERC



Figure 1: System block diagram of the fully-integrated low-voltage AFE. The mixed-signal feedback loop comprises the analog circuits shown in white and digital processing shown with the shaded blocks.

Circuits for wearable vital sign monitors have very stringent requirements on power dissipation due to limited energy storage capacity.  Extending the time between battery recharge or device replacement requires low-power circuits.  This work focuses on the design of a fully-integrated, low-voltage, digitally-assisted analog front-end (AFE) for ambulatory ECG monitoring, and it builds on work described in ^[1] .  The power consumption of an AFE is often determined by dynamic range (DR) requirements.  For bio-potential acquisition, the high end of the DR requirement is often set by interference such as 50/60-Hz power-line interference (PLI) ^[2] .  Here, a mixed-signal interference cancellation loop is used to cancel PLI right at the input of the system, thus reducing the DR requirement to enable low-voltage operation.  The fully-integrated AFE shown in Figure 1 leverages techniques such as oversampling, digital processing, and delta-sigma noise shaping to reduce the system area and power.  A target supply voltage of 0.6V provides power savings from voltage scaling and ensures compatibility with state-of-the-art digital signal processors ^[3] to reduce system complexity.

1. J. L. Bohorquez, M. Yip, A. P. Chandrakasan and J. L. Dawson, “A digitally-assisted sensor interface for biomedical applications,” in Proc. IEEE Symp. on VLSI Circuits, Jun. 2010, pp. 217-218. [↩]
2. E. M. Spinelli and M. A. Mayosky, “Two-electrode biopotential measurements: Power line interference analysis,” IEEE Trans. Biomedical Engineering, vol. 52, no. 8, pp. 1436-1442, Aug. 2005. [↩]
3. J. Kwong and A. P. Chandrakasan, “An energy-efficient biomedical signal processing platform,” in Proc. IEEE European Solid-State Circuits Conference, Sep. 2010, pp. 526-529. [↩]