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Download as PDFDesign of Low-power FPGA using Integrated Graphene Interconnects
As process technology scales, the importance of material and architectural innovation for interconnect performance will continue to increase. Graphene has attracted much interest as a replacement for copper interconnects due to its high conductivity and high current-carrying capacity [1] [2] [3] . Graphene sheets are also an attractive alternative to carbon nanotube-based interconnects as they are more compatible with conventional lithography methods. The purpose of this project is to integrate graphene devices as redundant interconnects for a low-power field-programmable gate array (FPGA). Interconnect delay is a significant portion of the delay due to multiple routing segments in an FPGA. Furthermore, global interconnects have been shown to dominate the total power consumption in FPGAs [4] .
In this work, we monolithically integrate graphene interconnects on a prototype CMOS chip. Large-area graphene sheets are first grown by chemical vapor deposition [5] and transferred onto the CMOS chip. The large graphene sheet is then lithographically patterned and etched into interconnect wires. Each end of the graphene wire is electrically connected to the underlying transmitter/receiver pair. The test chip includes an FPGA with 5×5 array of logic blocks and 10-bit unidirectional buses. Most of the wire segments in between the core logic blocks and switch matrices are implemented in the CMOS metal layers. A total of 16 double-length wires use graphene, which interfaces to the switch matrices. Each segment has 4 redundant wires and a tester unit. The tester unit uses a coarse time-to-digital converter (TDC) to measure and convert the RC delay of the graphene wire into a 3-bit digital code. The TDCs have tunable resolution with a delay range between 1 ns and 20 µs.
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