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Download as PDFTime-interleaved Zero-crossing Based ADC
In zero-crossing based circuits (ZCBC), op-amps in pipelined ADCs are replaced with zero-crossing detectors (ZCDs). The closed-loop feedback provided by the op-amp is replaced with a semi-open-loop switched-capacitor structure [1] [2] [3] [4] . The power efficiency of ZCBC has been demonstrated in various pipelined ADC designs [1] [2] [3] [4] .
Time-interleaving can be applied to most ADC architectures to increase the overall sampling rate. The combined ADC’s accuracy and dynamic performance is limited by the matching between the different ADC channels. Mismatch in the offset, gain, and sampling time skew of the ADC channels degrade the combined signal to noise and distortion ratio (SNDR). In this work, we implemented a time-interleaved zero-crossing based (ZCB) time-interleaved ADC. The core pipelined ADC design is similar to the work presented in [4] . The interchannel interference through the reference voltage is reduced by the reference precharging scheme. The timing skew between channels is calibrated by foreground calibration.
In this time-interleaved ADC, the gain mismatch and the offset mismatch between the ADCs are measured and removed digitally. The offset is measured with a zero input and removed digitally. The gain error is measured by measuring the peak to peak values when the ADC is driven with a full-scale sine wave. The ADC code of each channel is digitally scaled to remove the gain error. The timing skew is also measured and corrected using variable delay elements. In the measurement results, the ADC achieves 8.7 ENOB and 61 dB SFDR with a 211-MHz input signal while sampling at 450 MS/s. The ADC uses a 1.2-V supply and consumes 34 mW. This result corresponds to a figure of merit of 182 fJ/step.
- J. K. Fiorenza, T. Sepke, P. Holloway, C. G. Sodini, and H.-S. Lee, “Comparator based switched capacitor circuits for scaled CMOS Technologies,” IEEE Journal of Solid-State Circuits, vol. 41, no. 12, Dec. 2006, pp. 2658 – 2668. [↩] [↩]
- L. Brooks and H.-S. Lee, “A zero-crossing based 8b 200MS/s pipelined ADC,” IEEE ISSCC Dig. Tech. Papers, Feb. 2007, pp. 460-461. [↩] [↩]
- L. Brooks and H.-S. Lee, “A 12b 50MS/s fully differential zero-crossing based ADC without CMFB,” ISSCC Dig. Tech. Papers, Feb. 2009, pp. 166-167. [↩] [↩]
- J. Chu, L. Brooks, and H.-S. Lee, “A zero-crossing based 12b 100MS/s pipelined ADCs with decision boundary gap estimation calibration,” IEEE VLSI Circuits Dig. Tech Papers, June 2010, pp. 237-238. [↩] [↩] [↩]