All entries for Chi-Sang Poon

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Chi-Sang Poon

• Title: Principal Research Scientist
• Department: Harvard-MIT Division of Health Sciences and Technology

Collaborators

• K. Zhou, Intel
• T. Mak, Newcastle University
• K.-P.Lam, Chinese University of Hong Kong

Postdoctoral Associate

• Y. Meng

Support Staff

• Y. Ning, Tech. Asst.

Publications

Terrence Mak, Raaed Al-Dujaily, Kuan Zhou, Yicong Meng, Alex Yakovlev, Chi-Sang Poon, Dynamic programming networks for large-scale 3D chip integration, IEEE Circuits and Systems Magazine, pp 1-8, 2012 (in press)

Mak, T.,   Kai-Pui Lam,  Ng, H.S., Rachmuth, G., Chi-Sang Poon.  A CMOS Current-Mode Dynamic Programming Circuit IEEE Transactions on Circuits and Systems I-REGULAR PAPERS Volume: 57 Issue: 12   Pages: 3112-3123, Published: DEC 2010

Rachmuth G, Zhou K, Monzon JJC, Helble H, Poon CS. A picoampere A/D converter for biosensor applications. Sensors and Actuators B-CHEMICAL Volume: 149   Issue: 1   Pages: 170-176   Published: AUG 6 2010

Rachmuth G, Poon CS. Transistor analogs of emergent iono-neuronal dynamics. HFSP Journal Volume: 2   Issue: 3   Pages: 156-166 Published: JUN 2008

On-chip Dynamic Programming Networks Design in TSV-Based 3D Stacking Technology

• Authors: T. Mak, R. Al-Dujaily, K. Zhou, K.-P. Lam, C.-S. Poon

Recent technological advances in three-dimensional (3D) semiconductor fabrication have provided an implementation platform for powerful multicore, multiprocessor, and network-on-chip (NoC) systems. As the communication complexity grows significantly with the number of computational, control, and memory units, design considerations and the provision for efficient interconnection in large-scale system will be critical. We have developed an on-chip distributed dynamic-programming (DP) network ^[1] of transitivity computation on a 3D grid stack. Such type of network can be reconfigured for shortest path computation for finding optimal interconnected paths ^{[1] [2]} and with a range of applications including dynamic routing ^[3] , deadlock detection ^[4] and fault-tolerance ^[4] . This abstract presents the design of a dynamic programming network, implemented in a fully stacked 3-layer 3D through silicon via (TSV) 150-nm CMOS technology. This DP-network contains a 4×4×3 three-dimensional network. Three silicon layers contain a compact network of interconnected computational units. The vertical inter-unit communication is achieved by means of TSV, and the mesh interconnection provides a natural minimal area overhead associated with this communication. The prototype circuit measures 2 mm×2 mm. Test results demonstrated the effectiveness of such a DP-network for deadlock detection, and the computational delay is less than 10 ns for detecting deadlock from a large-scale network. This work provides promising results for future networks-on-chip applications using 3D embedded DP-network.

1. T. Mak, K. P. Lam, H. S. Ng, G. Rachmuth, and C.-S. Poon, “A CMOS current-mode dynamic programming circuit,” IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 57, pp. 3112-3123, 2010. [↩] [↩]
2. K.-P. Lam, T. Mak, and C.-S. Poon, “Simulation of large-scale dynamic programming networks on 3D implementation platform,” presented at the Proc. of TENCON, Fukuoka, Japan, 2010. [↩]
3. T. Mak, K.-P. Lam, P. Cheung, and W. Luk, “Adaptive routing in network-on-chips using a dynamic programming network,” IEEE Trans. Industrial Electronics, accepted for publication. [↩]
4. R. Al-Dujaily, T. Mak, F. Xia, A. Yakovlev, and M. Palesi, “Run-time deadlock detection in networks-on-chip using coupled transitive closure networks,” presented at DATE – Design, Automation and Test in Europe, Grenoble, France, 2011. [↩] [↩]