Bias Stress Effect in PbS Quantum Dot Field Effect Transistors
- Category: Electronic Devices
- Tags: Tim Osedach, Vladimir Bulovic
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Download as PDFIn recent years, there has been an increasing interest in the use of PbS and PbSe quantum dots (QDs) for optoelectronic device applications. Much remains poorly understood about charge transport in thin films of these materials, however. In several recent studies of lead chalcogenide QDs in field effect transistor (FET) structures, a fast bias stress effect, or shift in threshold voltage (ΔVth) under prolonged gate bias, was observed [1] [2] [3] [4] . This effect manifests as a stretched-exponential decay in the drain-source current (Ids) and is usually attributed to screening of the gate field by the trapped charge. The instability associated with bias stress precludes many practical applications of FETs and complicates the characterization of their performance. Moreover, the dynamics of the stressing process in QD-FETs have not been quantitatively characterized and uncertainty remains regarding the physical origin for the trapped charge, such as whether it accumulates at the QD/dielectric interface or within the QD film itself.
We investigated the bias stress effect in ethanedithiol (EDT)-treated PbS QD films in a top-gate bottom-contact field effect transistor (FET) configuration (see Figure 1). Devices exhibit ambipolar operation with typical mobilities on the order of μe = 4×10-3 cm2 V-1 s-1 and μh = 3×10-4 cm2 V-1 s-1. A fast stress effect is observed in both n-channel and p-channel operation (Figure 2). Similar stress and recovery characteristics are observed in devices made with a variety of dielectrics, including parylene-C, PMMA and polystyrene, suggesting that the bias stress effect is a bulk phenomenon and not due to the semiconductor/dielectric interface. At room temperature, stress and recovery characteristics are found to be consistent with the presence of deep electron traps and shallow hole traps with densities on the order of at least 0.5 traps-per-QD. Study of bias stress at low temperature (T=78 K), however, reveals a freeze-out of the effect which cannot be simply explained by the presence of traps.
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- Figure 1: Schematic of top-gate bottom-contact device structure.
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- Figure 2: Drain-source current during stress and recovery for a typical device.
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