At the prestigious 2006 International Solid States Circuit Conference (ISSCC), researchers from Massachusetts Institute of Technology (MIT) will present an ultra low power (ULP) 256 kilobit static random access memory (SRAM) test device manufactured in Texas Instruments' (NYSE: TXN) (TI) advanced 65-nm CMOS process.
Developed for battery-operated devices where high performance and low power are critical, the SRAM features the industry's lowest reported voltage, and is being considered for TI's SmartReflex(TM) power management technologies for extending battery life of mobile products.
The resulting 0.4 volt sub-threshold SRAM achieves 2.25 times lower leakage power compared to its 6T counterpart at 0.6 volts. By leveraging smaller feature sizes of TI's 65-nm process, the 256kb SRAM incorporates 10 transistors per bitcell to enable operation down to 400mV.
"Ultra low power operation is critical in a variety of emerging commercial and military applications," said Prof. Anantha P. Chandrakasan of MIT. "With funding from DARPA and TI, MIT graduate students have developed ultra-lowvoltage logic and memory circuits in 65-nm CMOS that function below 400mV. Scaling to such low supply voltages is critical to minimum energy processing and enables Ultra-Dynamic Voltage Scaling (U-DVS). The goal of this ULP technology is to reduce energy by an order of magnitude with minimal loss in system performance."
MIT's Sub-Threshold Circuits Group
Based upon a multi-year collaboration between TI and MIT, and partially funded by the Defense Advanced Research Projects Agency (DARPA), the SRAM development is part of a larger objective to create Ultra Low Power (ULP) logic and memory for battery-operated devices. The joint program is focused on reducing voltages to the sub-threshold level to save much-needed energy and enable simultaneous ULP and high performance, and includes development of memory modules and others such as logic and switching mode power supplies (SMPS).
The MIT work includes analysis of the optimal energy point of a given system, modeling energy characteristics of sub-threshold circuits and developing circuit styles and architectures. Research is focused on emerging applications, where energy efficiency concerns now supercede the traditional emphasis on speed.
Extending SmartReflex Technologies
The jointly developed MIT-TI SRAM device is based upon TI's advanced 65-nm process that integrates several techniques to address the industry's heightened emphasis on lowering power. For wireless applications in particular, multimedia and other advanced functionality are increasing processing demands, and steps to reduce power and manage heat dissipation are critical. TI's solution is SmartReflex dynamic power management technologies that automatically scales power supply voltage based on users performance demands and helps control power consumption.
By monitoring circuit speed, SmartReflex technologies dynamically adjust voltages to meet exact performance requirements without sacrificing overall system performance. This ensures that minimum power is used for each operating frequency, extending battery life and reducing the amount of heat produced by the device. Adjusting voltages to sub-threshold levels in the 256kb SRAM further demonstrates and extends capabilities of the SmartReflex approach.
"TI is proud to be part of MIT's world class research and visionary ULP design techniques that are so critical for future mobile SoC products," said Dr. Uming Ko, TI Senior Fellow and Director of TI's Wireless Chip Technology Center. "By leveraging these techniques in future mobile SoC designs, TI will extend its abilities to enable new wireless entertainment, communications and connectivity features, and deliver higher quality, longer lasting mobile experiences."
About TI's 65-nm Process
In December TI qualified its advanced 65-nm process technology and moved to volume manufacturing. The TI 65-nm process delivers more processing performance for advanced applications in a smaller space without increasing power consumption. TI is leading the volume ramp to production for 65-nm process technology with volume product delivery across its targeted markets, including wireless communications.
TI first disclosed the process technology in early 2004, and announced sampling of the industry's first 65-nm wireless digital baseband processor in March 2005. The process technology doubles transistor density over the company's 90-nm process, shrinking equivalent designs by half and boosting transistor performance by up to 40 percent. In addition to reducing leakage power from idle transistors, TI's 65-nm process can simultaneously integrate hundreds of millions of transistors that support both analog and digital functions in System on Chip (SoC) configurations.
* DARPA has provided approval for public release, distribution unlimited.
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