<\/a>Figure 1: Comparison with the state-of-the-art (data adopted from B. Murmann, \u201cADC Performance Survey 1997-2012,” http:\/\/www. stanford.edu\/~murmann\/adcsurvey.html).<\/p><\/div>\n
A. H. Chang, H.-S. Lee, D. S. Boning
\nSponsorship: Masdar Institute of Science and Technology<\/p>\n
There is a growing demand for low-power, high-speed and high-resolution A\/D converters for applications such as wideband wired\/wireless communication, software radio and millimeter-wave imaging systems. For many years, the successive-approximation-register (SAR) ADC has appeared mostly in the low-speed and low-power applications. The unprecedented improvement in speed and energy efficiency of scaled CMOS technologies helps expand the SAR architecture into the median-to-high-speed application domains that are traditionally designed using the flash or pipelined architectures. Along with other benefits, such as good digital compatibility, excellent power, and area efficiency and rail-to-rail input swings, the SAR architecture has become one of the more popular topologies.<\/p>\n
Recent SAR designs have demonstrated outstanding bandwidth (running at hundreds of MS\/s to GS\/s range) and superior energy efficiency (with FoM 100f<\/i>J\/conv.-step), but the resolution is limited to less than 10b ENOB. While scaling benefits speed and power efficiency, it does not improve capacitor matching, and the reduced supply headroom makes designing high-resolution ADC more difficult. Moreover, reference voltage settling also places a stringent settling requirement that limits the maximum operating speed. This work introduces redundancy and calibration into the design to help alleviate the settling and the mismatch problems. A sub-radix-2 SAR ADC is presented here with several new contributions. First, we incorporate the tri-level based switching[