{"id":1826,"date":"2013-07-25T18:24:45","date_gmt":"2013-07-25T18:24:45","guid":{"rendered":"https:\/\/mtlsites.mit.edu\/annual_reports\/2013\/?p=1826"},"modified":"2013-08-13T20:25:33","modified_gmt":"2013-08-13T20:25:33","slug":"designing-complex-digital-systems-with-scaled-nano-electro-mechanical-relays","status":"publish","type":"post","link":"https:\/\/mtlsites.mit.edu\/annual_reports\/2013\/designing-complex-digital-systems-with-scaled-nano-electro-mechanical-relays\/","title":{"rendered":"Designing Complex Digital Systems with Scaled Nano-electro-mechanical Relays"},"content":{"rendered":"

Silicon CMOS circuits have a well-defined lower limit on their achievable energy efficiency due to sub-threshold leakage. Once this limit is reached, power constrained applications will face a cap on their maximum throughput independent of their level of parallelism. Avoiding this roadblock requires an alternative device with a steeper sub-threshold slope, i.e., lower VDD<\/sub>\/Ion<\/sub> for the same Ion<\/sub>\/Ioff<\/sub>. One promising class of such devices is electrostatically actuated nano-electro-mechanical (NEM) switches with nearly ideal Ion<\/sub>\/Ioff<\/sub> characteristics. Although mechanical movement makes NEM switches significantly slower than CMOS, they can be useful for a wide range of VLSI applications if we reexamine traditional system- and circuit-level design techniques to take advantage of the electrical properties of the device.<\/p>\n

Basic circuit design techniques and functionality of some main building blocks of VLSI systems, such as logic, memory, and clocking structures, have been demonstrated in our previous works[1<\/a>]<\/sup>[2<\/a>]<\/sup>[3<\/a>]<\/sup>. Recently, by employing pass-transistor logic design, we have designed and demonstrated complex relay-based arithmetic units such as multipliers (Figure 1b-c)[4<\/a>]<\/sup>. Simulation results of an optimized 16-bit relay multiplier built in a 90-nm equivalent relay process model predict ~10x improvement in energy-efficiency over optimized CMOS designs in the 10-100 MOPS performance range. The relative performance of the multiplier enhancements are in line with what was previously predicted by a NEM relay 32-bit adder[3<\/a>]<\/sup>, suggesting that complete VLSI systems, such as a microprocessor, would expect to see similar energy\/performance improvements from adopting NEM relay technology[3<\/a>]<\/sup>,[4<\/a>]<\/sup>.<\/p>\n

Since scaling is crucial for performance, energy, and total area improvement, we have developed a scaled version of the original relay, a 6-terminal relay, which is 25x smaller and offers enhanced functionality. The operation of the main building block of the NEM-relay based multiplier, the (7:3) compressor, built with these scaled devices is experimentally demonstrated. This circuit, consisting of 46 scaled relays, is the largest scaled relay circuit successfully tested to date (Figure 2).<\/p>\n\n\t\t